Systems and methods for circuit testing using LBIST
AssigneeKabushiki Kaisha Toshiba
InventorNaoki Kiryu
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AssigneeKabushiki Kaisha Toshiba
InventorNaoki Kiryu
Estimating the term…
Systems and methods for performing logic built-in-self-tests (LBISTS) in digital circuits. In one embodiment, the operation of LBIST circuitry is suspended at the end of each test cycle so that the bit patterns generated by the functional logic of the device under test can be examined to determine if any errors occurred during the test cycle. Pseudorandom bit patterns are scanned into the scan chains interposed between portions of the functional logic circuit and then propagated through the functional logic. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of the scan chains. The bit patterns are processed and compared to corresponding data generated by a parallel LBIST system in a device that is known to operate properly. The LBIST test cycles are then halted if there are errors in the generated bit patterns or resumed if there are no errors.
A method for performing a series of test cycles using pseudorandom patterns of bits in a logic built-in self test (LBIST) system, wherein the LBIST system includes a plurality of scan chains and a pseudorandom pattern generator (PRPG), wherein the plurality of scan chains extend between portions of functional logic of a device under test and are connected to each other through the portions of functional logic, each of the scan chains including a plurality of scan latches disposed correspondingly to levels of functional logic, and wherein the PRPG is coupled to the plurality of scan chains and configured to generate pseudorandom patterns of bits to be scanned into the scan chains, the method comprising, in each of the test cycles:
A logic built-in self test (LBIST) system comprising:
A system comprising:
Dependencies are inferred from the claim text.