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US 7,627,797 B2Granted
Test access port
AssigneeIntel Corporation
InventorsDavid E. Miner, Steven J. Tu, Scott W. Murray
Life of this patent
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Abstract
A method, apparatus, and system are provided for testing multi-core processors. The testing includes a test control mechanism and a multi-core processor including a set of cores with at least one core having a test access port controller (TAPC), distributed data, and a set of distributed control registers. The multi-core processor and the test control mechanism further having a configuration to provide testing the multi-core processor. The test control mechanism is modified to simultaneously test multiple cores.
Claims23
An apparatus comprising:
- at least one test control mechanism;
- a multi-core processor including a plurality of cores, wherein at least one core includes a test access port controller (TAPC), a plurality of distributed data registers and a plurality of distributed control registers;
- and
- said multi-core processor and said test control mechanism having a configuration so as to allow testing of said multi-core processor, said test control mechanism tests more than one core of the plurality of cores concurrently.
1 more element
A system comprising:
- a computing platform, including:
- a memory to store instructions;
- a multi-core processor to process instructions, said multi-core processor including:
- a test control mechanism,
- a plurality of processor cores,
- at least one circuit comprising non-processor core logic, and
- wherein at least one processor core includes a test access port controller (TAPC), a plurality of distributed data registers and a plurality of distributed control registers;
- and
- said multi-core processor and said test control mechanism having a configuration so as to allow testing of said plurality of processor cores, said test control mechanism tests more than one processor core of the plurality of processor cores concurrently.
6 more elements
A method comprising:
- providing an indicator to identify a desired testing option;
- based upon said desired testing option, dynamically routing signals between a plurality of test access ports (TAPs) during testing,
- wherein said plurality of TAPs are part of a multi-core processor;
- and
- said multi-processor core including a plurality of processor cores,
- wherein at least one processor core includes a test access port controller (TAPC), a plurality of distributed data registers and a plurality of distributed control registers.
3 more elements
Dependencies are inferred from the claim text.