Pipelined data processor with deterministic signature generation

In a data processing system, a method comprising:

• during operation of the data processing system, entering a test mode;
• capturing test data and generating a deterministic signature in a multiple input shift register (MISR) during the test mode, while receiving and handling exceptions during the test mode;
• in response to acknowledging an interrupt request signal while in the test mode, using an enabling clock signal to keep the MISR enabled while capturing into the MISR a portion that is less than all of normal instruction execution results existing in a pipeline of the data processing system;
• flushing a remainder of the normal instruction execution results existing in the pipeline of the data processing system in response to acknowledging the interrupt request signal;
• disabling the MISR with the enabling clock signal;
• processing and completing execution of an exception associated with the interrupt request signal without capturing results from exception processing in the MISR;
• returning to instruction execution associated with the test mode with the MISR enabled by the enabling clock signal;
• and
• using the deterministic signature generated during the test mode to test functionality of circuitry within the data processing system.

In a pipelined data processing system, a method comprising:

• providing functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry;
• providing at least one staging storage element associated with a pipeline stage of the pipelined data processing system, the at least one staging storage element receives test data directly from the plurality of test points when the system is in a test mode;
• providing a multiple input shift register (MISR) which receives test data from the at least one staging storage element and provides a MISR result;
• in response to acknowledging an interrupt request signal while in the test mode, using an enabling clock signal to keep the MISR enabled while capturing into the MISR a portion that is less than all of normal instruction execution results existing in a pipeline of the pipelined data processing system;
• discarding a remainder of the normal instruction execution results existing in the pipeline of the data processing system in response to acknowledging the interrupt request signal;
• disabling the MISR with the enabling clock signal;
• processing and completing execution of an exception associated with the interrupt request signal without capturing results from exception processing in the MISR;
• and
• returning to instruction execution associated with the test mode with the MISR enabled by the enabling clock signal.

A method of testing a data processor comprising:

• providing circuitry for placing the data processor in a test mode of operation;
• providing circuitry for enabling and disabling a multiple input shift register (MISR) to capture data in the multiple input shift register to create a test value when the data processor is in the test mode of operation;
• providing circuitry for selectively blocking enablement of the multiple input shift register (MISR) during at least a portion of exception processing performed by the data processor when the data processor was placed in the test mode of operation prior to exception processing;
• in response to acknowledging an interrupt request signal while in the test mode of operation, using an enabling clock signal to keep the MISR enabled while capturing into the MISR a portion that is less than all of normal instruction execution results existing in a pipeline of the data processor;
• discarding a remainder of the normal instruction execution results existing in the pipeline of the data processor in response to acknowledging the interrupt request signal;
• disabling the MISR with the enabling clock signal;
• processing and completing execution of an exception associated with the interrupt request signal without capturing results from exception processing in the MISR;
• and
• returning to instruction execution associated with the test mode with the MISR enabled by the enabling clock signal.