Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems

A method of characterizing a communications channel within a high speed memory system of the type in which a first signal having an easily recognized repeating pattern is combined with a second signal having a pseudo-random pattern to produce a combined signal and transmitting said combined signal over a bus of a memory system, comprising:

• receiving said combined signal from the memory system bus, said combined signal having a disruptive signal transition pattern to challenge the communications channel;
• removing said second signal from said received combined signal to produce a received first signal;
• and
• examining said signal pattern of said received first signal to determine if said easily recognized repeating pattern is present.

An apparatus for producing a signal for characterizing a communications channel within a high speed memory system, comprising:

• a generator for generating a first signal having an easily recognized repeating pattern;
• a generator for generating a second signal having a pseudo-random pattern;
• a first circuit for combining said first and second signals to produce a combined signal having a disruptive signal transition pattern to challenge the communications channel;
• a transmitter for transmitting said combined signal from a processor to a memory device over a bus of a memory system.

An apparatus for characterizing a communications channel within a high speed memory system of the type in which a first signal having an easily recognized repeating pattern is combined with a second signal having a pseudo-random pattern to form a combined signal and transmitting said combined signal over a bus of a memory system, said apparatus comprising:

• a receiver for receiving said combined signal, said combined signal having a disruptive signal transition pattern to challenge the communications channel;
• a circuit for removing said second signal from said received combined signal to produce a received first signal;
• and
• circuitry for examining the pattern of said received first signal.

A memory system of the type having a memory controller communicating with a plurality of memory devices through a communications channel, said memory controller comprising;

• a generator for generating a first signal having an easily recognized repeating pattern;
• a generator for generating a second signal having a pseudo-random pattern;
• a first circuit for combining said first and second signals to produce a combined signal, said combined signal having a disruptive signal transition pattern to challenge the communications channel;
• and
• a transmitter for transmitting said combined signal over a bus of a memory system, said plurality of memory devices each comprising:
• a receiver for receiving said combined signal;
• a second circuit for removing said second signal from said received combined signal to produce a received first signal;
• and
• a circuit for examining the pattern of said received first signal.