Logic circuit and semiconductor integrated circuit

A semiconductor device comprising:

• a first delay circuit, which is inputted with a first signal and is capable of setting a delay time by using a third signal to output a fifth signal;
• a second delay circuit, which is inputted with a second signal and is capable of setting a delay time by using a fourth signal to output a sixth signal;
• a delay identifying circuit, which is inputted with a fifth signal and a sixth signal, and generates a seventh signal having a different number of pulses between in the case where the fifth signal is delayed than the sixth signal and in the case where the sixth signal is delayed than the fifth signal;
• a logic circuit, which is inputted with the seventh signal and a eighth signal, and outputs a ninth signal;
• and
• a counter, which is inputted with the ninth signal and a tenth signal, and output an eleventh signal,
• wherein the logic circuit is controlled with the eighth signal which determines a period in which the number of pulses of the seventh signal is counted, and the counter is reset with the tenth signal.

A semiconductor device comprising:

• a first input terminal, which is inputted with a first signal;
• a second input terminal, which is inputted with a second signal;
• a first logic circuit connected to the first input terminal and the second input terminal, and comprising a memory circuit which is in a holding state either in a period in which the first signal is Low and the second signal is High, or a period in which the first signal is High and the second signal is Low;
• and
• a second logic circuit, which is inputted with the first signal, the second signal, and an output signal of the first logic circuit, and generates a third signal having different number of pulse between in the case where the first signal is delayed than the second signal and in the case where the second signal is delayed than the first signal.

A semiconductor device comprising:

• a first input terminal, which is inputted with a first signal;
• a second input terminal, which is inputted with a second signal;
• a first delay circuit connected to the first input terminal, wherein the first delay circuit is inputted with the first signal and a sixth signal, and is capable of setting a delay time by using the sixth signal to output a fourth signal;
• a second delay circuit connected to the second input terminal, wherein the second delay circuit is inputted with the second signal and a seventh signal, and is capable of setting a delay time by using the seventh signal to output a fifth signal;
• and
• a logic circuit, which is inputted with the fourth signal and the fifth signal and generates a third signal.

A semiconductor device comprising:

• a first input terminal, which is inputted with a first signal;
• a second input terminal, which is inputted with a second signal;
• a first delay circuit connected to the first input terminal, wherein the first delay circuit is inputted with the first signal and is capable of setting a delay time to output a fourth signal;
• a second delay circuit connected to the second input terminal, wherein the second delay circuit is inputted with the second signal and is capable of setting a delay time to output a fifth signal;
• a first logic circuit inputted with the fourth signal and the fifth signal, and comprising a memory circuit which is in a holding state either in a period in which the fourth signal is Low and the fifth signal is High, or a period in which the fourth signal is High and the fifth signal is Low;
• and
• a second logic circuit, which is inputted with the fourth signal, the fifth signal, and an output signal of the first logic circuit, and generates a third signal having different number of pulse between in the case where the fourth signal is delayed than the fifth signal and in the case where the fifth signal is delayed than the fourth signal.