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US 7,627,772 B2Granted
Fast data access mode in a memory device
AssigneeMicron Technology, Inc.
InventorDean Nobunaga
Life of this patent
Estimating the term…
Abstract
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.
Claims18
A fast data access circuit comprising:
- a delay circuit for generating a delayed clock signal, from a plurality of selectable time delays, in response to an input clock signal and a delay control signal;
- a control circuit coupled to the delay circuit and generating a mode control signal and the delay control signal in response to a configuration word loaded from address lines;
- a multiplexing circuit for selecting between the input clock signal and the delayed clock signal and outputting a selected clock in response to the mode control signal;
- and
- a data first-in-first-out (FIFO) register, coupled to the multiplexing circuit and input data, for outputting the input data at a rate dependant on the selected clock.
2 more elements
A fast data access circuit comprising:
- a mode/configuration register coupled to address input signals and generating a mode control signal in response to a loaded configuration word from the address input signals;
- a delay circuit coupled to an input clock signal and the mode/configuration register, the delay circuit providing, in response to the loaded configuration word and an input clock signal, a delayed clock signal from a plurality of selectable time delays selected by the configuration word;
- a multiplexing circuit for outputting a selected clock signal in response to the mode control signal selecting between the input clock signal and the delayed clock signal and;
- control logic for generating a plurality of register control signals in response to the selected clock signal;
- and
- a first-in-first-out data output register, coupled to the control logic and stored data, for outputting the stored data at a rate responsive to the plurality of register control signals.
3 more elements
A non-volatile memory device comprising:
- an array of non-volatile memory cells for storing a plurality of data bits;
- a plurality of address inputs coupled to the array of non-volatile memory cells;
- and
- a selectable data rate access circuit coupled to the array of non-volatile memory cells and the plurality of address inputs, the circuit comprising:
- a delay circuit for generating a delayed clock signal, from a plurality of selectable time delays, in response to an input clock signal and a delay control signal;
- a control circuit coupled to the delay circuit and the plurality of address inputs and generating a mode control signal and the delay control signal in response to a configuration word from the plurality of address inputs;
- a multiplexing circuit coupled to the input clock signal and the delayed clock signal and outputting a selected clock in response to the mode control signal;
- and
- a first-in-first-out data output register, coupled to the multiplexing circuit and input data, for outputting the input data at a data rate dependant on the selected clock.
6 more elements
A memory system comprising:
- a processor for generating memory signals including address signals;
- and
- a non-volatile memory device, coupled to the processor, for storing and accessing data in response to the memory signals, the device comprising:
- an array of non-volatile memory cells for storing a plurality of data bits;
- a plurality of address inputs coupled to the address signals and the array of non-volatile memory cells;
- and
- a selectable data rate access circuit coupled to the array of non-volatile memory cells and the plurality of address inputs, the circuit comprising:
- a delay circuit for generating a delayed clock signal, from a plurality of selectable time delays, in response to an input clock signal and a delay control signal;
- a control circuit coupled to the delay circuit and the plurality of address inputs and generating a mode control signal and the delay control signal in response to a configuration word from the plurality of address inputs;
- a multiplexing circuit coupled to the input clock signal and the delayed clock signal and outputting a selected clock in response to the mode control signal;
- and
- a first-in-first-out data output register, coupled to the multiplexing circuit and input data, for outputting the input data at a data rate dependant on the selected clock.
9 more elements
Dependencies are inferred from the claim text.