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US 7,627,770 B2Granted
Apparatus and method for automatic low power mode invocation in a multi-threaded processor
AssigneeMIPS Technologies, Inc.
InventorDarren M. Jones
Life of this patent
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AssigneeMIPS Technologies, Inc.
InventorDarren M. Jones
Estimating the term…
A processor comprises a processor core executing multiple threads. A bifurcated thread scheduler includes an internal processor core component and an external processor core component. The bifurcated thread scheduler identifies when all of the multiple threads are blocked and thereafter automatically enters a default low power sleep mode.
A processor, comprising:
A computer readable storage medium, comprising executable instructions to:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
To perform miscellaneous control operations, e.g. NOP: thread control instructions
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
Recovery, e.g. branch miss-prediction, exception handling: using multiple copies of the architectural state, e.g. shadow registers
Term ended 5 Jul 2026 (estimated)
This application is related to the following Non-Provisional U.S. Patent Applications, each of which is incorporated by reference in its entirety for all purposes:
Ser. No. (Docket No.) Filing Date Title 10/684,350 Oct. 10, 2003 MECHANISMS FOR ASSURING (MIPS.0188-01-US) QUALITY OF SERVICE FOR PROGRAMS EXECUTING ON A MULTITHREADED PROCESSOR 10/929,342 Aug. 27, 2004 INTEGRATED MECHANISM FOR (MIPS.0189-01-US) SUSPENSION AND DEALLOCTION OF COMPUTATIONAL THREADS OF EXECUTION IN A PROCESSOR 10/928,746 Aug. 27, 2004 APPARATUS, METHOD AND (MIPS.0192-00-US) INSTRUCTION FOR INITIATION OF CONCURRENT INSTRUCTION STREAMS IN A MULTITHREADING MICROPROCESSOR 10/929,102 Aug. 27, 2004 MECHANISMS FOR DYNAMIC (MIPS.0193-00-US) CONFIGURATION OF VIRTUAL PROCESSOR RESOURCES 10/929,097 Aug. 27, 2004 APPARATUS, METHOD, AND (MIPS.0194-00-US) INSTRUCTION FOR SOFTWARE MANAGEMENT OF MULTIPLE COMPUTATIONAL CONTEXTS IN A MULTITHREADED MICROPROCESSOR 10/954,988 Sep. 30, 2004 SYNCHRONIZED STORAGE (MIPS.0195-00-US) PROVIDING MULTIPLE SYNCHRONIZATION SEMANTICS 10/955,231 Sep. 30, 2004 SMART MEMORY BASED (MIPS.0196-00-US) SYNCHRONIZATION CONTROLLER FOR A MULTI-THREADED MULTIPROCESSOR SOC 11/051,997 Feb. 4, 2005 BIFURCATED THREAD SCHEDULER (MIPS.0199-00-US) IN A MULTITHREADING MICROPROCESSOR 11/051,980 Feb. 4, 2005 LEAKY-BUCKET THREAD (MIPS.0200-00-US) SCHEDULER IN A MULTITHREADING MICROPROCESSOR 11/051,979 Feb. 4, 2005 MULTITHREADING (MIPS.0201-00-US) MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY 11/051,998 Feb. 4, 2005 MULTITHREADING PROCESSOR (MIPS.0201-01-US) INCLUDING THREAD SCHEDULER BASED ON INSTRUCTION STALL LIKELIHOOD PREDICTION 11/051,978 Feb. 4, 2005 INSTRUCTION/SKID BUFFERS IN A (MIPS.0202-00-US) MULTITHREADING MICROPROCESSOR 11/087,070 Mar. 22, 2005 INSTRUCTION DISPATCH (MIPS.0208-00-US) SCHEDULER EMPLOYING ROUND- ROBIN APPARATUS SUPPORTING MULTIPLE THREAD PRIORITIES FOR USE IN MULTITHREADING MICROPROCESSOR 11/086,258 Mar. 22, 2005 RETURN DATA SELECTOR (MIPS.0209-00-US) EMPLOYING BARREL-INCREMENTER- BASED ROUND-ROBIN APPARATUS 11/087,063 Mar. 22, 2005 FETCH DIRECTOR EMPLOYING (MIPS.0210-00-US) BARREL-INCREMENTER-BASED ROUND-ROBIN APPARATUS FOR USE IN MULTITHREADING MICROPROCESSOR 11/087,064 Mar. 22, 2005 BARREL-INCREMENTER-BASED (MIPS.0204.00US) ROUND-ROBIN APPARATUS AND INSTRUCTION DISPATCH SCHEDULER EMPLOYING SAME FOR USE IN MULTITHREADING MICROPROCESSOR Apr. 14, 2005 APPARATUS AND METHOD FOR (MTEC-022/00US) SOFTWARE SPECIFIED POWER MANAGEMENT PERFORMANCE USING LOW POWER VIRTUAL THREADS
The present invention relates generally to power management in a multithreaded processor. More particularly, the invention relates to a technique for automatically invoking a low power mode processor state.
The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a multithreading microprocessor that may be used in accordance with an embodiment of the invention.
FIG. 2 illustrates a bifurcated scheduler, including a dispatch scheduler and a policy manager, utilized in accordance with an embodiment of the invention.
Like reference numerals refer to corresponding parts throughout the several views of the drawings.
FIG. 1 illustrates a pipelined multithreading microprocessor 100 according to an embodiment of the invention. This exemplary multithreading microprocessor 100 is used to disclose concepts of the invention. It should be appreciated that the concepts of the invention may also be applied to alternate multithreading microprocessor designs.
The microprocessor 100 is configured to concurrently execute a plurality of threads. A thread—also referred to herein as a thread of execution, or instruction stream—comprises a sequence, or stream, of program instructions. The threads may be from different programs executing on the microprocessor 100, or may be instruction streams from different parts of the same program executing on the microprocessor 100, or a combination thereof.