External memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy level
AssigneeNVIDIA Corporation
InventorsMonier Maher, Jean Pierre Bordes, Christopher Lamb, Sanjay J. Patel
Life of this patent
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Abstract
An integrated circuit comprises an external memory, a plurality of parallel connected Vector Processing Engines (VPEs), and an External Memory Unit (EMU) providing a data transfer path between the VPEs and the external memory. Each VPE contains a plurality of data processing units and a message queuing system adapted to transfer messages between the data processing units and other components of the integrated circuit.
Claims17
A parallel integrated circuit that accesses an external memory, comprising:
- a control processor;
- a plurality of parallel connected Vector Processing Engines (VPEs), wherein each one of the VPEs comprises a plurality of Vector Processing Units (VPUs), a plurality of VPU Control Units (VCUs), a Direct Memory Access (DMA) controller, and a VPE messaging unit (VMU) that is coupled between the plurality of VPUs, the plurality of VCUs, the DMA controller, and the control processor, wherein the VMU includes a first scheduler that is configured to schedule transfers of messages between the plurality of VPUs and the plurality of VCUs and a second scheduler that is configured to schedule transfers of DMA requests received from the plurality of VPUs and the plurality of VCUs to the DMA controller based on occupancy levels of DMA completion notification receive queues to prevent DMA completion notifications from blocking the DMA requests;
- and,
- an External Memory Unit (EMU) that is coupled between the external memory, the control processor, and the DMA controller within each VPE in the plurality of VPEs.
A Physics Processing Unit (PPU) that accesses an external memory storing at least physics data, comprising:
- a PPU control engine (PCE) comprising a programmable PPU control unit (PCU);
- a plurality of parallel connected Vector Processing Engines (VPEs), wherein each one of the VPEs comprises:
- a plurality of Vector Processing Units (VPUs), each comprising a grouping of mathematical/logic units adapted to perform computations on physics data for a physics simulation;
- a plurality of VPU Control Units (VCUs);
- a Direct Memory Access (DMA) subsystem comprising a DMA controller;
- and, a VPE messaging unit (VMU) adapted to transfer messages between the plurality of VPUs, the plurality of VCUs, the DMA subsystem, and the PCE, wherein the VMU includes a first scheduler that is configured to schedule transfers of messages between the plurality of VPUs and the plurality of VCUs and a second scheduler that is configured to schedule transfers of DMA requests received from the plurality of VPUs and the plurality of VCUs to the DMA controller based on occupancy levels of DMA completion notification receive queues to prevent DMA completion notifications from blocking the DMA requests;
- and,
- an External Memory Unit (EMU) that is coupled between the external memory, the PCE, and the DMA controller within each VPE in the plurality of VPEs.
Dependencies are inferred from the claim text.