Method and circuit implementation for multiple-word transfer into/from memory subsystems

A circuit for moving multiple words between a memory subsystem and a processor register file in response to a multi-word transfer instruction which specifies an access type information, a consecutive register group based on a pair of information, a mask selection information and a base register information for a starting address of corresponding memory locations in the memory subsystem, wherein the mask selection information indicates at least one of a plurality of special registers to be selected, and the special registers comprises a general data pointer, a frame pointer, a function call return pointer, and a stack pointer, and the circuit comprising:

• a register index calculator, generating a register index and a base modification indication signal based on the consecutive register group information, the mask selection information and the base register information;
• an read/write controller, for generating a memory access control signal to the memory and a register access control signal to the processor register file, in response to the access type information and the base modification indication signal;
• and a bidirectional selection unit, bi-directionally forwarding the multiple words between the memory subsystem and the processor register file, based on the memory access control signal and the register access control signal, wherein the multi-word transfer instruction further specifies:
• an address update mode for indicating to update the memory address consecutively;
• an order mode for indicating whether the memory access is performed before or after each update of the memory address;
• and a modification mode for indicating whether to modify the base register in the end of the instruction execution as last-updated memory address, further comprising:
• an arithmetic operation unit, for updating the memory address in response to the address update mode, a next address register, for temporarily storing the updated memory address from the arithmetic operation unit, a first multiplexer, for selecting between an initial memory address of the memory locations and an output of the next address register, and a second multiplexer, for selecting between an output of the arithmetic operation unit and an output of the first multiplexer.