Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system

A processor comprising:

• an instruction source that stores instructions;
• a fetcher coupled to the instruction source, that fetches instructions from the instruction source to provide an instruction stream that includes one or more fetched branch instructions;
• a branch execution unit, coupled to the fetcher that speculatively executes one or more of the fetched branch instructions by using branch prediction information and that resolves whether or not a branch in the speculatively executed branch instruction is taken, thus providing one or more executed branch instructions;
• and
• a throttle controller, coupled to the fetcher capable of throttling the fetching of instructions by the fetcher the throttle controller including:
• a branch instruction queue, having a plurality of entries, that stores the one or more fetched branch instructions from the instruction stream, wherein each of the one or more branch instructions occupies one of the entries, and wherein the recently stored one or more branch instructions is designated as valid, meaning that the branch instruction is still in process;
• the branch instruction queue having a head pointer for dynamically pointing to a newest, valid, branch instruction in response to a branch instruction being stored in the branch instruction queue, and a tail pointer dynamically pointing to an oldest, valid, branch instruction stored in the branch instruction queue, such that any branch instructions positioned between the head pointer and the tail pointer are valid;
• a valid vector for designating as invalid the one or more executed branch instructions in the branch instruction queue;
• the branch instruction queue for moving the tail pointer such that the tail pointer points to the oldest, valid, branch instruction stored in the branch instruction queue;
• a confidence storage memory that stores a confidence value describing an amount of confidence in the branch prediction information for each fetched branch instruction stored in the branch instruction queue;
• an adder for summing the confidence values of the branch instruction positioned from the head pointer to the tail pointer stored in the branch instruction queue, thus generating a confidence value total for valid branch instructions only;
• and
• the throttle controller throttling the fetching of instructions from the instruction source if the confidence value total indicates confidence less than a predetermined confidence threshold, wherein the throttling reduces power consumption by the processor.

An information handling system (IHS), the IHS comprising:

• a memory;
• a processor coupled to the memory, the processor including:
• an instruction source that stores instructions, the instruction source being coupled to the memory;
• a fetcher coupled to the instruction source, that fetches instructions from the instruction source to provide an instruction stream that includes one or more fetched branch instructions;
• a branch execution unit, coupled to the fetcher that speculatively executes one or more of the fetched branch instructions by using branch prediction information and that resolves whether or not a branch in the speculatively executed branch instruction is taken, thus providing one or more executed branch instructions;
• and
• a throttle controller, coupled to the fetcher capable of throttling the fetching of instructions by the fetcher the throttle controller including:
• a branch instruction queue, having a plurality of entries, that stores the one or more fetched branch instructions from the instruction stream, wherein each of the one or more branch instructions occupies one of the entries, and wherein the recently stored one or more branch instructions is designated as valid, meaning that the branch instruction is still in process;
• the branch instruction queue having a head pointer for dynamically pointing to a newest, valid, branch instruction in response to a branch instruction being stored in one of the entries, and a tail pointer for dynamically pointing to an oldest, valid, branch instruction stored in one of the entries, such that any branch instructions positioned between the head pointer and the tail pointer are valid;
• a valid vector for designating as invalid the one or more executed branch instructions in the entries of the branch instruction queue;
• the branch instruction queue for moving the tail pointer such that the tail pointer points to the oldest, valid, branch instruction stored in the entries of the branch instruction queue;
• a confidence storage memory that stores a respective confidence value for each of the fetched branch instruction in the branch instruction queue, the confidence values describing a lack of confidence in the branch prediction information for respective fetched branch instructions in the branch instruction queue;
• an adder for summing the confidence value of the branch instructions positioned from the head pointer to the tail pointer stored in the branch instruction queue, thus generation a confidence value total for valid branch instructions only;
• and
• the throttle controller throttling the fetching of instructions from the instruction source if the confidence value total in the confidence storage memory exceeds a predetermined threshold, wherein the throttling reduces power consumption by the processor.