Instruction processing circuit including freezing circuits for freezing or passing instruction signals to sub-decoding circuits

An instruction processing circuit comprising:

• an instruction source for producing successive instructions;
• an execution circuit having operand inputs for receiving operands selected by the instructions and a control input for controlling execution of operations applied to the operands;
• and
• an instruction decoder having an instruction input coupled to the instruction source and a control output coupled to the control input of the execution circuit, the instruction decoder being arranged to generate successive control signals at the control output under control of respective ones of the instructions, the instruction decoder comprising:
• a plurality of sub-decoding circuits coupled in parallel between the instruction input and the control output, each for generating control signals for a respective type of instruction;
• input freezing circuits, each coupled between the instruction input and a respective one of the sub-decoding circuits, each freezing circuit having a control input, each freezing circuit being arranged to freeze or pass instruction signals to its respective one of the sub-decoding circuits under control of its control input;
• and
• a predecoding circuit with an input coupled to the instruction input and outputs coupled to the control inputs of the freezing circuits, and arranged to detect to which type of instruction a supplied instruction belongs, and to control, dependent on the detected type, to which of the sub-decoding circuits instruction information derived from the supplied instruction will be passed and to which of the sub-decoding circuits supply of instruction information derived from a previously supplied instruction will be frozen;
• wherein at least one of the freezing circuits comprises a freezing register with an input and an output, and a multiplexer with a first input coupled to the instruction source, a second input coupled to the output of the freezing register, an output coupled to the input of the freezing register and to the sub-decoding circuit that is coupled to the freezing circuit, and a control input coupled to the predecoding circuit.