Optimization of a hardware resource shared by a multiprocessor

A device comprising:

• (a) a first processor having an associated first hardware resource;
• (b) a second processor having an associated second hardware resource;
• (c) a computer-readable storage medium configurable by a given instruction group and by an optimization page;
• and
• (d) a control unit implemented in a hardware-logic and operable to
• (i) apply a first hardware resource management strategy to the first hardware resource, the first resource management policy being an optimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially optimal manner, facilitate an execution of the given instruction group by the first processor, and acquire a first execution context corresponding to the first processor during the execution;
• (ii) apply a second hardware resource management strategy to the second hardware resource, the second resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group, facilitate an execution of the given instruction group in the second processor, and acquire a second execution context corresponding to the second processor during the execution;
• (iii) select a hardware resource management strategy likely to provide a substantially optimum execution of the given instruction group from the first hardware resource management strategy and the second hardware resource management strategy;
• and
• (iv) logically associate in the computer-readable storage medium the given instruction group and the optimization page, the optimization page configured to indicate the selected hardware resource management strategy and the execution context corresponding to the processor that executed the given instruction group during the application of the selected hardware resource management strategy as set forth above.

A computer program product comprising:

• (a) program instructions operable to perform a process in a computing device, the process comprising:
• (i) applying a first hardware resource management strategy to a first hardware resource associated with a first processor, executing a given instruction group in the first processor, the first resource management policy being an optimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially optimal manner, and acquiring a first execution context corresponding to the first processor during the execution;
• (ii) applying a second hardware resource management strategy to a second hardware resource associated with a second processor, executing the given instruction group in the second processor, the second resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group, and acquiring a second execution context corresponding to the second processor during the execution;
• (iii) selecting a hardware resource management strategy likely to provide a substantially optimum execution of the given instruction group from the first hardware resource management strategy and the second hardware resource management strategy;
• and
• (iv) facilitating a logical association in a computer-readable storage medium between the given instruction group and an optimization page, the optimization page indicative of the selected hardware resource management strategy and the acquired execution context corresponding to the processor that executed the given instruction group during the application of the selected hardware resource management strategy as set forth above;
• and
• (b) the computer-readable storage medium bearing the program instructions.

A method comprising:

• applying a first test hardware resource management strategy to a first hardware resource associated with a first processor, implementing a first possible substantially optimum execution of a given instruction group in the first processor, the first test hardware resource management policy being an optimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially optimal manner, and acquiring a first execution context corresponding to the first processor during the first possible substantially optimum execution of the given instruction group;
• applying a second test hardware resource management strategy to a second hardware resource associated with a second processor, the second test hardware resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group, implementing a second possible substantially optimum execution of the given instruction group in the second processor, and acquiring a second execution context corresponding to the second processor during the second possible substantially optimum execution of the given instruction group;
• selecting a hardware resource management strategy likely to provide a substantially optimum execution of the given instruction group from the first test hardware resource management strategy and the second test hardware resource management strategy;
• and
• saving an association of the given instruction group and an optimization page in a storage device, the optimization page indicative of the selected test hardware resource management policy and the acquired execution context corresponding to the processor that executed the given instruction group during the application of the selected test hardware resource management strategy as set forth above.