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US 7,627,737 B2Granted
Processing element and method connecting registers to processing logic in a plurality of configurations
AssigneeMicron Technology, Inc.
InventorGraham Kirsch
Life of this patent
Estimating the term…
Abstract
A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighborhood connection register configured to receive data from and send data to other processing elements. The connections between the result registers and between the result registers and the neighborhood connection register are selectively configurable by applied control signals.
Claims22
A processing element for a parallel processor, comprising:
- processing logic;
- first and second result registers each of which has an input and an output;
- a neighborhood connection register;
- a register connection selection circuit coupled to the processing logic and to the result registers, the register connection selection circuit including a feedback signal path structured to selectively couple the output of the second result register to the input of the first result register to allow a result of a processing operation stored in the second result register to be fed back to the first result register;
- and
- a neighborhood connection register selection circuit coupled to the neighborhood connection register and at least one of the first and second result registers, the register connection selection circuit being responsive to a first control signal, and the neighborhood connection register selection circuit being responsive to a second control signal, the register connection selection circuit and the neighborhood connection register being configured to selectively couple the first and second result registers, the processing logic and the neighborhood connection register to each other in a plurality of different configurations, each of the different configurations having a different order in which at least some of the first and second result registers, the processing logic and the neighborhood connection register are coupled to each other.
3 more elements
An active memory system, comprising:
- a memory device;
- a host processor;
- and
- a processing element coupled to the memory device and the host processor, the processing element comprising:
- processing logic;
- first and second result registers;
- a neighborhood connection register;
- a register connection selection circuit coupled to the processing logic and to the result registers the register connection selection circuit including a feedback signal path structured to selectively couple the output of the second result register to the input of the first result register to allow a result of a processing operation stored in the second result register to be fed back to the first result register;
- and
- a neighborhood connection register selection circuit coupled to the neighborhood connection register and at least one of the first and second result registers, the register connection selection circuit being responsive to a first control signal, and the neighborhood connection register selection circuit being responsive to a second control signal, the register connection selection circuit and the neighborhood connection register being configured to selectively couple the first and second result registers, the processing logic and the neighborhood connection register to each other in a plurality of different configurations. each of the different configurations having a different order in which at least some of the first and second result registers, the processing logic and the neighborhood connection register are coupled to each other.
7 more elements
A processing element for a parallel processor, comprising:
- i. processing logic;
- ii. first and second result registers each of which has an input and an output;
- iii. a neighborhood connection register;
- iv. a register connection selection circuit coupled to the processing logic and to the result registers, the register connection selection circuit including a feedback signal path structured to selectively couple the output of the second result register to the input of the first result register to allow a result of a processing operation stored in the second result register to be fed back to the first result register;
- and
- v. a register connection selection circuit being responsive to a first control signal, and the neighborhood connection register selection circuit being responsive to a second control signal;
- the register connection selection circuit and the neighborhood connection register being configured to selectively couple the first and second result registers, the processing logic and the neighborhood connection register to each other in a plurality of different configurations, each of the different configurations having a different order in which at least some of the first and second result registers, the processing logic and the neighborhood connection register are coupled to each other.
4 more elements
An active memory system, comprising:
- vi. a memory device;
- vii. a host processor;
- and
- viii. a processing element coupled to the memory device and the host processor, the processing element comprising:
- ix. processing logic;
- x. first and second result registers;
- xi. a neighborhood connection register;
- xii. a register connection selection circuit coupled to the processing logic and to the result registers, the register connection selection circuit including a feedback signal path structured to selectively couple the output of the second result register to the input of the first result register to allow a result of a processing operation stored in the second result register to be fed back to the first result register;
- and
- xiii. a register connection selection circuit being responsive to a first control signal, and the neighborhood connection register selection circuit being responsive to a second control signal;
- the register connection selection circuit and the neighborhood connection register being configured to selectively couple the first and second result registers, the processing logic and the neighborhood connection register to each other in a plurality of different configurations, each of the different configurations having a different order in which at least some of the first and second result registers, the processing logic and the neighborhood connection register are coupled to each other.
8 more elements
An active memory system, comprising:
- a memory device;
- a host processor;
- and
- a processing element coupled to the memory device and the host processor, the processing element comprising:
- processing logic;
- first and second result registers;
- a neighborhood connection register;
- a register connection selection circuit coupled to the processing logic and to the result registers, the register connection selection circuit including a feedback signal path structured to selectively couple the output of the second result register to the input of the first result register to allow a result of a processing operation stored in the second result register to be fed back to the first result register;
- and
- the register connection selection circuit being responsive to a first control signal, and the neighborhood connection register selection circuit being responsive to a second control signal;
- the register connection selection circuit and the neighborhood connection register being configured to selectively couple the first and second result registers, the processing logic and the neighborhood connection register to each other in a plurality of different configurations, each of the different configurations having a different order in which at least some of the first and second result registers, the processing logic and the neighborhood connection register are coupled to each other.
8 more elements
Dependencies are inferred from the claim text.