System and method for optimizing a memory controller
AssigneeSun Microsystems, Inc.
InventorLaurent R. Moll
Life of this patent
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Abstract
A system and method for optimizing a memory controller. The system includes a memory controller and at least two registers for storing a plurality of operating contexts for the memory controller. The plurality of operating contexts is utilized by the memory controller to optimize the memory controller. According to the system and method disclosed herein, the operating contexts optimize the performance of the memory controller.
Claims27
A system comprising:
- a memory controller;
- a first register, wherein the first register is configured to store a first operating context, wherein the first operating context comprises a first set of timing parameters of the memory controller;
- and
- a second register, wherein the second register is configured to store a second operating context,
- wherein the second operating context comprises a second set of timing parameters of the memory controller,
- wherein the first and the second set of timing parameters each control a number of cycles required to execute instructions, such that the number of cycles is programmed to a desired number so that a time to complete a cycle is a desired time,
- wherein the memory controller is configured to use the second register while the first set of timing parameters are being modified in the first register, and
- wherein the first operating context is stored for a first operating frequency, wherein the second operating context is stored for a second operating frequency, and wherein the second operating frequency is lower than the first operating frequency.
A method for optimizing a memory controller, the method comprising:
- operating the memory controller using a first register, wherein the first register comprises a first operating context, wherein the first operating context comprises a first set of timing parameters of the memory controller;
- and
- while operating the memory controller using the first register, programming a second operating context in a second register, wherein the second operating context comprises a second set of timing parameters of the memory controller,
- wherein programming the second operating context comprises programming a number of cycles required to execute instructions, so that a time to complete a cycle is a desired time, and
- wherein the first operating context is stored for a first operating frequency, wherein the second operating context is stored for a second operating frequency, and wherein the second operating frequency is lower than the first operating frequency.
A computer-readable storage medium containing program instructions for optimizing a memory controller, the program instructions which when executed by a computer system cause the computer system to execute a method comprising:
- operating the memory controller using a first register, wherein the first register comprises a first operating context, wherein the first operating context comprises a first set of timing parameters of the memory controller;
- and
- while operating the memory controller using the first register, programming a second operating context in a second register, wherein the second operating context comprises a second set of timing parameters of the memory controller,
- wherein programming the second operating context comprises programming a number of cycles required to execute instructions, so that a time to complete a cycle is a desired time, and
- wherein the first operating context is stored for a first operating frequency, wherein the second operating context is stored for a second operating frequency, and wherein the second operating frequency is lower than the first operating frequency.
Dependencies are inferred from the claim text.