Atomic memory operators in a parallel processor

An apparatus for updating data in memory while executing multiple threads of instructions comprising:

• an instruction unit for decoding a single instruction from one of a plurality of concurrently executing threads of instructions;
• a memory buffer;
• a plurality of execution units coupled to the instruction unit and the memory buffer, the memory being shared by the plurality of execution units, the execution units capable of receiving the single instruction, and in response to the single instruction received, reading data from a specific memory location in the memory buffer, performing an operation involving the data read from the memory location to generate a result, and storing the result to the specific memory location, without requiring separate load and store instructions;
• and
• wherein the execution unit is further capable of, in response to the single instruction received, precluding another one of the plurality of threads of instructions from altering data at the specific memory location while reading of the data from the specific memory location, performing the operation involving the data, and storing the result to the specific memory location,
• wherein each execution unit is allocated a portion of the memory, and
• wherein an execution unit of the plurality of execution units is selected to execute the instruction, the execution unit being selected from the plurality of execution units if a memory address associated with the first instruction falls within an address range associated with the portion of memory allocated to the execution unit.

A system for updating data in memory while executing multiple threads of instructions, the system comprising:

• means for receiving a single instruction from one of a plurality of concurrently executing threads of instructions;
• means for, in response to the single instruction received, reading data from a specific memory location, performing an operation involving the data read from the memory location to generate a result, and storing the result to the specific memory location, without requiring separate load and store instructions, wherein the single instruction is forwarded to an execution unit of a plurality of execution units capable of maintaining exclusive control of the memory location in a memory shared by the plurality of execution units, wherein the execution unit reads the data from the specific memory location, performs the operation involving the data read from the memory location to generate the result, and stores the result to the specific memory location, wherein each execution unit is allocated a portion of the memory, and wherein the execution unit to which instruction is forwarded is selected from the plurality of execution units if a memory address associated with the first instruction falls within an address range associated with the portion of memory allocated to the execution unit;
• and
• means for, in response to the single instruction received, precluding another one of the plurality of threads of instructions from altering data at the specific memory location while reading of the data from the specific memory location, performing the operation involving the data, and storing the result to the specific memory location.