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US 7,627,718 B2Granted
Frozen ring cache
AssigneeIntel Corporation
InventorsVincent J. Zimmer, Michael A. Rothman
Life of this patent
Estimating the term…
Abstract
A processor having multiple cores and a multiple cache segments, each core associated with one of the cache segments, the cache segments interconnected by a data communication ring, and logic to disallow operation of the ring at a startup event and to execute an initialization sequence at one or more of the cores so that each of the one or more of the cores operates using the cache segment associated with the core as a read-write memory during the initialization sequence
Claims19
A processor comprising:
- a plurality of cores and a plurality of cache segments, each core associated with one of the cache segments;
- the cache segments interconnected by a data communication ring;
- and
- logic to disallow operation of the ring at a startup event and to execute an initialization sequence at one or more of the cores so that each of the one or more of the cores operates using the cache segment associated with the core as a read-write memory during the initialization sequence.
1 more element
A method performed at a startup event of a processor based system comprising:
- disallowing operation of a data communication ring interconnecting a plurality of processor cores of a processor of the system and a plurality of cache segments of the processor, each core associated with one of the cache segments;
- and
- executing an initialization sequence at one or more of the cores so that each of the one or more of the cores operates using the cache segment associated with the core as a read-write memory during the initialization sequence.
A system comprising:
- a processor, the processor further comprising a plurality of cores and a plurality of cache segments, each core associated with one of the cache segments;
- the cache segments interconnected by a data communication ring;
- and
- logic to disallow operation of the ring at a startup event and to execute an initialization sequence at one or more of the cores so that each of the one or more of the cores operates using the cache segment associated with the core as a read-write memory during the initialization sequence.
1 more element
Dependencies are inferred from the claim text.