Addressing scheme for neural modeling and brain-based devices using special purpose processor
AssigneeNeurosciences Research Foundation, Inc.
InventorsJames A. Snook, Richard W. Schermerhorn
Life of this patent
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Abstract
A special purpose processor (SPP) can use a Field Programmable Gate Array (FPGA) to model a large number of neural elements. The FPGAs or similar programmable device can have multiple cores doing presynaptic, postsynaptic, and plasticity calculations in parallel. Each core can implement multiple neural elements of the neural model.
Claims6
A special purpose processor which implements a synthetic neural model being a collection of the biological anatomy of selected areas of a human brain, the biological anatomy being the physical properties of neural elements of the anatomy of the brain, the special purpose processor comprising:
- a) a plurality of cores, each of said cores comprising a separate neural processing unit, each said neural processing unit for processing and performing calculations on data modeling a plurality of the neural elements;
- b) memory for storing data corresponding to the biological anatomy of the brain, including data representing
- (i) synaptic weights of synaptic connections of each neural element,
- (ii) post synaptic potential outputs of each of said neural elements of each said core, and
- (iii) synaptic connection tables identifying anatomical connections of the neural elements of the synthetic neural model;
- c) a bus structure for interconnecting said memory with each of said plurality of cores and for connecting each of said plurality of cores with one another;
- d) a finite state machine controller for controlling said plurality of cores and said memory to communicate over said bus structure, in which said cores are implemented to process the data in parallel and perform calculations on the data, said finite state machine controller being implemented to cause the special purpose processor, over a given respective timeslice, to,
- (i) read and transfer the data from said memory to said cores,
- (ii) control said cores to process in parallel the read data, and
- (iii) return the data processed by said cores to said memory in preparation for processing the data over a succeeding timeslice;
- and
- e) an addressing controller, responsive to said finite state machine controller, for addressing said memory and said cores for reading and writing data by said memory and for processing data by said cores in each said given respective timeslice, wherein said addressing controller causes addressed data to be transferred in a predetermined order so that said memory knows which one or more of said cores is a source of the data in a said given respective timeslice.
Dependencies are inferred from the claim text.