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US 7,627,462 B2Granted
Hardware simulation using a test scenario manager
AssigneeArm Limited
InventorAndrew Mark Nightingale
Life of this patent
Estimating the term…
Abstract
A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.
Claims27
Apparatus for simulating data processing operations performed by a data processing apparatus, said apparatus comprising:
- a hardware simulator responsive to one or more stimulus signals to generate one or more response signals simulating a response of said data processing apparatus to said one or more stimulus signals if applied to said data processing apparatus;
- a plurality of signal interface controllers coupled to said hardware simulator, each signal interface controller serving to perform one or more simulation actions transferring at least one of one or more stimulus signals and one or more response signals between a corresponding portion of said hardware simulator and said signal interface controller as part of simulating said data processing operations;
- a test scenario manager coupled to said plurality of signal interface controllers and operable to transfer test scenario controlling messages to said plurality of signal interface controllers, at least one of said test scenario controlling messages including:
- (i) data defining a simulation action to be performed by a signal interface controller;
- and
- (ii) data defining when said signal interface controller should perform said simulated action;
- and
- a time generator coupled to said plurality of signal interface controllers and said test scenario manager for generating messages specifying time defining events corresponding to advancement of simulated time for said hardware simulator,
- wherein said test scenario manager includes a shared data memory into which a signal interface controller may store data using a test scenario controlling message sent from said signal interface controller to said test scenario manager via said shared data memory independently of advancement of simulated time by said messages specifying time defining events, said data being readable from said shared data memory by another signal interface controller.
6 more elements
A method of simulating data processing operations performed by a data processing apparatus, said method comprising the steps of:
- in response to one or more stimulus signals, using a hardware simulator to generate one or more response signals simulating a response of said data processing apparatus to said one or more stimulus signals if applied to said data processing apparatus;
- performing in each of a plurality of signal interface controllers coupled to said hardware simulator one or more simulation actions transferring at least one of one or more stimulus signals and one or more response signals between a corresponding portion of said hardware simulator and said signal interface controller as part of simulating said data processing operations;
- and
- transferring test scenario controlling messages from a test scenario manager to said plurality of signal interface controllers, at least one of said test scenario controlling messages including:
- (i) data defining a simulation action to be performed by a signal interface controller;
- and
- (ii) data defining when said signal interface controller should perform said simulated action;
- and
- generating messages specifying time defining events corresponding to advancement of simulated time for said hardware simulator,
- wherein said test scenario manager includes a shared data memory into which a signal interface controller may store data using a test scenario controlling message sent from said signal interface controller to said test scenario manager, said data being readable from said shared data memory by another signal interface controller,
- whereby said test scenario controlling messages are communicated via said shared data memory independently of advancement of simulated time by said messages specifying time defining events.
8 more elements
A computer program product embodied on a computer-readable medium and comprising code that when executed controls a computer to simulate data processing operations performed by a data processing apparatus, said computer program product comprising:
- hardware simulator code responsive to one or more stimulus signals to generate one or more response signals simulating a response of said data processing apparatus to said one or more stimulus signals if applied to said data processing apparatus;
- a plurality of signal interface controller code blocks coupled to said hardware simulator code, each signal interface controller code block serving to perform one or more simulation actions transferring at least one of one or more stimulus signals and one or more response signals between a corresponding portion of said hardware simulator code and said signal interface controller code block as part of simulating said data processing operations;
- and
- test scenario manager code coupled to said plurality of signal interface controller code blocks and operable to transfer test scenario controlling messages to said plurality of signal interface controller code blocks, at least one of said test scenario controlling messages including:
- (i) data defining a simulation action to be performed by a signal interface controller code block;
- and
- (ii) data defining when said signal interface controller code block should perform said simulated action;
- and
- time generator code coupled to said plurality of signal interface controller blocks and said test scenario manager code for generating messages specifying time defining events corresponding to advancement of simulated time for said hardware simulatorcode,
- wherein said test scenario manager code provides a shared data memory into which a signal interface controller code block may store data using a test scenario controlling message sent from said signal interface controller code block to said test scenario manager code, said data being readable from said shared data memory by another signal interface controller code block,
- whereby said test scenario controlling messages are communicated via said shared data memory independently of advancement of simulated time by said messages specifying time defining events.
8 more elements
Dependencies are inferred from the claim text.