US 7,627,188 B2 · Error diffusion method and hardware architecture

Abstract

A system and method for performing threshold stamping are disclosed. First and second threshold values corresponding to first and second pixels may be retrieved from a threshold memory. A plurality of upscaled threshold values may optionally be computed based on the first threshold value and the second threshold value. An (upscaled) threshold value may be updated at each of one or more first register blocks. A binary pixel value may be computed based at least in part on the first updated threshold value. The first updated threshold value may be updated at each of one or more second register blocks. A downscaled threshold value may optionally be computed based on a plurality of second updated threshold values. The downscaled threshold value or second updated threshold value may be damped in a damping circuit, and the damped threshold value may be stored in the threshold memory.

Claims8

Dependent claims

A system for performing threshold stamping, the system comprising:

a threshold memory comprising a plurality of threshold values;
an error memory comprising a plurality of error values;
a register array, wherein the register array comprises a plurality of register blocks, wherein a first register block is in communication with the threshold memory and the error memory, wherein a second register block comprises an error diffusion block, wherein a third register block is in communication with the error memory, wherein the third register block outputs a stamped threshold value;
and
a threshold damping circuit, wherein the threshold damping circuit is in communication with the third register block and the threshold memory, wherein the threshold damping circuit reduces the stamped threshold value.

2 more elements

Dependencies are inferred from the claim text.

Error diffusion method and hardware architecture

Life of this patent

Error diffusion method and hardware architecture

Life of this patent

Abstract

Claims8