Shift register circuit and image display apparatus having the same
AssigneeMitsubishi Electric Corporation
InventorYouichi Tobita
Life of this patent
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Abstract
In a shift register circuit, a reduction of a driving capability caused by an increased operating rate is prevented. A shift register circuit includes a first transistor between an output terminal and a clock terminal, a second transistor between the output terminal and a first power-supply terminal, and a third transistor between the gate of the first transistor and a second power-supply terminal. The shift register circuit further includes a fourth transistor that charges the gate node of the third transistor on the basis of a signal inputted to a first input terminal, and a capacitive element that boosts the gate node of the third transistor that has been charged.
Claims23
A shift register circuit comprising:
- a clock terminal and an output terminal;
- a first transistor that supplies to said output terminal a first clock signal inputted to said clock terminal;
- a second transistor that discharges said output terminal;
- a third transistor that supplies a potential at a first power-supply terminal to a first node to which a control electrode of said first transistor is connected thereby charging said first node so as to turn on said first transistor;
- a first charging circuit that charges a second node to which a control electrode of said third transistor is connected, on the basis of a signal imputed to a given first input terminal;
- and
- a first boosting circuit that boosts said second node that has been charged, on the basis of a signal inputted to a given second input terminal.
An image display apparatus having a gate line driving circuit formed of a shift register circuit having multiple stages comprising a plurality of cascade- connected shift register circuits, wherein each of said multiple stages is a shift register circuit comprising:
- a clock terminal and an output terminal;
- a first transistor that supplies to said output terminal a first clock signal inputted to said clock terminal;
- a second transistor that discharges said output terminal;
- a third transistor that supplies a potential at a first power-supply terminal to a first node to which a control electrode of said first transistor is connected thereby charging said first node so as to turn on said first transistor;
- a first charging circuit that charges a second node to which a control electrode of said third transistor is connected, on the basis of a signal inputted to a given first input terminal;
- and
- a first boosting circuit that boosts said second node that has been charged, on the basis of a signal inputted to a given second input terminal.
Dependencies are inferred from the claim text.