Method of detecting the relative positioning of two signals and corresponding device
AssigneeSTMicroelectronics S.r.l.
InventorsXavier Cauchy, Eric Salvaire, Cédric Force
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Abstract
A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic signal generator for generating a phase logic signal from the two clock signals by assigning a predetermined logic value to the phase logic signal when a rising edge of the fast clock signal matches a predetermined location of the slow clock signal.
Claims17
A method of detecting a relative positioning of two clock signals comprising a fast clock signal having a fast clock frequency and a slow clock signal having a slow clock frequency, and where the fast clock frequency is n times greater than the slow clock frequency, and n comprises an integer greater than 1, the method comprising:
- generating a phase logic signal having a first logic value when a rising edge of the fast clock signal is situated at one of a rising edge and a falling edge of the slow clock signal;
- and
- multiplexing data based upon the phase logic signal.
A method of detecting a relative positioning of two clock signals comprising a fast clock signal having a fast clock frequency and a slow clock signal having a slow clock frequency, and where the fast clock frequency is n times greater than the slow clock frequency, and n comprises an integer greater than 1, the method comprising:
- generating a phase logic signal having a first logic value when a rising edge of the fast clock signal is situated at a one of a rising edge and a falling edge of the slow clock signal, wherein the generation of the phase logic signal comprises
- autosampling one of the two clock signals to obtain a first intermediate logic signal,
- sampling the first intermediate logic signal with the other clock signal so as to obtain a second intermediate logic signal, and
- performing a logic operation on the first and second intermediate signals to obtain the phase logic signal;
- and
- multiplexing data based upon the phase logic signal.
A device for detecting a relative positioning of two clock signals comprising a fast clock signal having a fast clock frequency and a slow clock signal having a slow clock frequency, and where the fast clock frequency is n times greater than the slow clock frequency, and n comprises an integer greater than 1, the device comprising:
- a phase logic signal generator comprising respective inputs for the fast and slow clock signals for generating a phase logic signal having a first logic value at an output when a rising edge of the fast clock signal is situated at a one of a rising edge and a falling edge of the slow clock signal;
- and
- a circuit cooperating with said phase logic signal generator for multiplexing data based upon the phase logic signal.
A device comprising:
- a phase logic signal generator comprising respective inputs for the fast and slow clock signals for generating a phase logic signal having a first logic value at an output when a rising edge of the fast clock signal is situated at a one of a rising edge and a falling edge of the slow clock signal;
- a circuit cooperating with said phase logic signal generator for synchronizing data transmission based upon said phase logic signal and for multiplexing data based upon the phase logic signal.
A device comprising:
- a phase logic signal generator comprising respective inputs for the fast and slow clock signals for generating a phase logic signal having a first logic value at an output when a rising edge of the fast clock signal is situated at one of a rising edge and a falling edge of the slow clock signal;
- and
- a circuit cooperating with said phase logic signal generator for controlled multiplexing of data based upon said phase logic signal.
A device comprising:
- a phase logic signal generator comprising respective inputs for the fast and slow clock signals for generating a phase logic signal having a first logic value at an output when a rising edge of the fast clock signal is situated at one of a rising edge and a falling edge of the slow clock signal;
- and
- a circuit comprising polyphase filters cooperating with said phase logic signal generator.
Dependencies are inferred from the claim text.