Digital transmit phase trimming
AssigneeRambus Inc.
InventorWilliam J. Dally
Life of this patent
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Abstract
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.
Claims25
A circuit, comprising:
- a multiplexer to receive input data signals on a plurality of first data lines and to output onto at least one second data line output data signals with transmit timing determined in accordance with a plurality of clock signals, the clock signals including an adjusted clock signal;
- a timing measurement circuit to:
- determine at least one timing parameter of at least one output data signal on at least the one second data line, and
- generate a control signal in accordance with a deviation of at least the one timing parameter from a desired value;
- and
- a phase adjustment circuit to adjust transmission of the at least one output data signal including adjusting a first clock signal of the plurality of clock signals in accordance with the control signal to generate the adjusted clock signal.
A method, comprising:
- using a multiplexer, coupling input data signals on a plurality of first data lines onto at least one second data line with transmit timing determined in accordance with a plurality of clock signals;
- determining at least one timing parameter of at least one output data signal on at least the one second data line;
- and
- adjusting transmission of the at least one output data signal including adjusting at least one of the clock signals in accordance with a deviation of at least the one timing parameter from a desired value.
A circuit, comprising:
- a multiplexer means to receive input data signals on a plurality of first data lines and to output onto at least one second data line output data signals with transmit timing determined in accordance with a plurality of clock signals, the clock signals including an adjusted clock signal;
- and
- a timing measurement means:
- to determine at least one timing parameter of at least one output data signal on at least the one second data line and
- to generate a control signal in accordance with a deviation of at least the one timing parameter from a desired value;
- and
- a phase adjustment means to adjust transmission of the at least one output data signal including adjusting a first clock signal of the plurality of clock signals in accordance with the control signal to generate the adjusted clock signal.
A computer readable storage medium containing data representing a circuit that includes:
- a multiplexer to receive input data signals on a plurality of first data lines and to output onto at least one second data line output data signals with transmit timing determined in accordance with a plurality of clock signals, the clock signals including an adjusted clock signal;
- and
- a timing measurement circuit:
- to determine at least one timing parameter of at least one output data signal on at least the one second data line and
- to generate a control signal in accordance with a deviation of at least the one timing parameter from a desired value;
- and
- a phase adjustment circuit to adjust transmission of the at least one output data signal including adjusting a first clock signal of the plurality of clock signals in accordance with the control signal to generate the adjusted clock signal.
Dependencies are inferred from the claim text.