Apparatus for data recovery in a synchronous chip-to-chip system

A memory system comprising:

• a memory device to issue a plurality of data signals and a strobe signal that transitions between valid logic levels when the data signals are present;
• data and strobe traces coupled to the memory device to convey the respective data and strobe signals;
• and
• a memory controller coupled to the memory device via the data and strobe traces to receive the data signals and the strobe signal, the memory controller including:
• a timing-reference node to receive a timing-reference signal;
• and
• a data-sampling apparatus coupled to the data and strobe traces and the timing-reference node, the data-sampling apparatus to phase adjust the timing-reference signal with phase information from the strobe signal to produce a data sampling signal;
• wherein the data-sampling apparatus includes a plurality of receivers each having a data input terminal, to receive one of the data signals;
• and
• wherein each of the receivers samples the respective one of the data signals using the data sampling signal.

A method for synchronizing receipt of read data signals from a memory device, the method comprising:

• receiving a strobe signal of a strobe phase from the memory device;
• comparing the strobe phase with a clock phase of a clock signal to generate phase information;
• phase shifting the clock signal per the phase information to generate a data sampling signal phase shifted with respect to the clock signal;
• and
• sampling the read data signals with the data sampling signal.

An integrated circuit chip comprising:

• means for receiving a strobe signal of a strobe phase and comparing the strobe phase with a clock phase of a clock signal to generate phase information;
• means for phase shifting the clock signal per the phase information to generate a data sampling signal phase shifted with respect to the clock signal;
• and
• a receiver to sample the read data signals with the data sampling signal.

A memory controller comprising:

• a. a clock line to convey a clock signal;
• b. a lock circuit having a lock-circuit input node coupled to the clock line, a lock-circuit phase-adjust node, and a lock-circuit output node, the lock circuit to provide a data sampling signal on the lock-circuit output node;
• c. a phase detector having a timing reference signal input node to receive a timing reference signal from a memory device, a feedback node to receive a feedback signal from the lock circuit, and a phase-detector output node coupled to the phase-adjust node of the lock circuit;
• and
• d. a receiver having a data input terminal, to receive a data signal from the memory device, and a data sampling signal input terminal coupled to the lock circuit output node to receive the data sampling signal;
• wherein the receiver samples the data signal with the data sampling signal.