Generating a clock crossing signal based on clock ratios
AssigneeSun Microsystems, Inc.
InventorsJurgen M. Schulz, Bharat K. Daga
Life of this patent
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Abstract
A multiple clock domain system. A system comprises two clock domains which receive a source clock signal. The first domain includes a first clock signal with a first frequency and the second domain includes a second clock signal with a second frequency. A ratio of the first frequency to the second frequency is N:M. The first domain is configured to initialize a count to N, if N is less than 2*M; and initialize the count to M, if N is not less than 2*M. Subsequently, on each cycle of the first clock signal, the first domain adds (M-N) to the count and asserts a sample enable signal, if the count is greater than or equal to N; and adds a value equal to M to the count and negates the sample enable signal, if the count is not greater than or equal to N.
Claims20
A data communications system comprising:
- a source clock signal;
- a first clock domain comprising a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency;
- and
- a second clock domain comprising a second clock signal which is derived from the source clock signal, wherein the second clock signal has a second frequency which is different from the first frequency, and wherein a ratio of the first frequency to the second frequency is N:M;
- wherein the first clock domain includes circuitry which is configured to:
- receive values indicative of N and M;
- initialize a count to N, in response to detecting N is less than 2*M;
- and
- initialize the count to M, in response to detecting N is not less than 2*M;
- wherein each cycle of the first clock signal, the circuitry is configured to:
- add a value equal to (M−N) to the count and assert a sample enable signal, in response to determining the count is greater than or equal to N;
- add a value equal to M to the count and negate the sample enable signal, in response to determining the count is not greater than or equal to N.
A method for generating a sample enable signal, the method comprising:
- receiving a source clock signal;
- generating a first clock signal with a first frequency in a first clock domain, wherein the first clock signal is derived from the source clock signal;
- generating a second clock signal with a second frequency in a second clock domain,
- wherein the second clock signal is derived from the source clock signal, and
- wherein the second clock signal has a second frequency which is different from the first frequency, and wherein a ratio of the first frequency to the second frequency is N:M;
- initializing a count to N, in response to detecting N is less than 2*M;
- initializing the count to M, in response to detecting N is not less than 2*M;
- each cycle of the first clock signal:
- adding a value equal to (M−N) to the count and asserting a sample enable signal, in response to determining the count is greater than or equal to N;
- adding a value equal to M to the count and negating the sample enable signal, in response to determining the count is not greater than or equal to N.
A circuit for generating a sample enable signal in a clock boundary crossing system, the circuit comprising:
- an interface configured to receive a source clock signal;
- an interface configured to receive values N and M, wherein N:M corresponds to a ratio of a first frequency of a first clock signal in a first clock domain to a second frequency of a second clock signal in a second clock domain;
- an interface configured to receive the first clock signal;
- a unit configured to:
- initialize a count to N, in response to detecting N is less than 2*M;
- and
- initialize the count to M, in response to detecting N is not less than 2*M;
- wherein each cycle of the first clock signal, circuitry configured to:
- add a value equal to (M−N) to the count and assert a sample enable signal, in response to determining the count is greater than or equal to N;
- add a value equal to M to the count and negate the sample enable signal, in response to determining the count is not greater than or equal to N.
Dependencies are inferred from the claim text.