US 7,627,031 B2Granted

Adaptive signal latency control for communications systems signals

AssigneeScintera Networks, Inc.

InventorsQian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov, Fabian Giroud

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Abstract

An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

Claims10

Dependent claims

An apparatus including adaptive circuitry for introducing a compensating signal latency related to a signal latency of a data symbol decision circuit, comprising:

a first signal terminal that conveys a pre-decision data signal having a data symbol period associated therewith;
a second signal terminal that conveys an error signal corresponding to a difference between an adaptive signal and a post-decision data signal which corresponds to and follows said pre-decision data signal by a first signal latency;
and
adaptive timing interpolation circuitry, coupled to said first and second signal terminals, that receives said error signal and in response thereto receives and adaptively processes said pre-decision data signal to provide said adaptive signal following said pre-decision data signal by a second signal latency related to said first signal latency, and includes
interpolating mixer circuitry, coupled to said first signal terminal, that receives and mixes an integrated signal and said pre-decision data signal to provide said adaptive signal,
phase detection circuitry, coupled to said second signal terminal and said interpolating mixer circuitry, that receives and detects a phase difference between said error signal and said adaptive signal to provide a detection signal, and includes
fractional delay circuitry, coupled to said interpolating mixer circuitry, that receives and delays said adaptive signal to provide a delayed signal corresponding to and following said adaptive signal by a fraction of said data symbol period, and
signal combining circuitry, coupled to said interpolating mixer circuitry, said fractional delay circuitry and said second signal terminal, that receives and combines said adaptive signal, said delayed signal and said error signal to provide said detection signal, and
signal integration circuitry, coupled to said phase detection circuitry and said interpolating mixer circuitry, that receives and integrates said detection signal to provide said integrated signal.

6 more elements

An apparatus including adaptive circuitry for introducing a compensating signal latency related to a signal latency of a data symbol decision circuit, comprising:

a first signal terminal that conveys a pre-decision data signal having a data symbol period associated therewith;
a second signal terminal that conveys an error signal corresponding to a difference between an adaptive signal and a post-decision data signal which corresponds to and follows said pre-decision data signal by a first signal latency;
and
adaptive timing interpolation circuitry, coupled to said first and second signal terminals, that receives said error signal and in response thereto receives and adaptively processes said pre-decision data signal to provide said adaptive signal following said pre-decision data signal by a second signal latency related to said first signal latency, and includes
interpolating mixer circuitry, coupled to said first signal terminal, that receives and mixes an integrated signal and said pre-decision data signal to provide said adaptive signal,
phase detection circuitry, coupled to said first and second signal terminals, that receives and detects a phase difference between said error signal and said pre-decision data signal to provide a detection signal, and includes
signal differentiation circuitry, coupled to said first signal terminal, that receives and differentiates said pre-decision signal to provide a differentiated signal, and
signal combining circuitry, coupled to said signal differentiation circuitry and said second signal terminal, that receives and combines said differentiated signal and said error signal to provide said detection signal, and
signal integration circuitry, coupled to said phase detection circuitry and said interpolating mixer circuitry, that receives and integrates said detection signal to provide said integrated signal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/186,241Filed 21 Jul 2005 · continuation
Priority: 17 Dec 2002
Published: US 2005/0271138 A18 Dec 2005
Granted: 1 Dec 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H04L 7/0062
Detection of the synchronisation error by features other than the received signal transition: detection of error based on data decision error,…
H04L 25/03057
Adaptive, i.e. capable of adjustment during data reception: with a recursive structure
H04L 7/0029
Correction by interpolation: interpolation of received data signal
H04L 2025/03503
Time-recursive: as a combination of feedback and prediction filters

Family

Application10/321,893Parent of this continuation · filed 17 Dec 2002
US 2005/0271138 A1Pre-grant publication · published 8 Dec 2005
US 6,922,440 B2Parent of this continuation
US 2004/0114700 A1Published application
US 7,627,031 B2This patent

From the US filing history. Foreign family members aren’t listed.