Method of creating optimized tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the same
AssigneeSamsung Electronics Co., Ltd.
InventorChae-Eun Rhee
Life of this patent
Estimating the term…
Abstract
Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.
Claims18
A method of creating a tile-switch mapping architecture comprising:
- multiplying a data communication flow from an arbitrary first tile k to an arbitrary second tile l by a hop distance value between arbitrary first and second switches i and j, in which the hop distance value of the first and second switches i and j is changed to the hop distance values of switches abutting the first tile k and switches abutting the second tile l, the multiplication is carried out for the changed hop distance values:
- summing the data communication flow multiplication results;
- multiplying a communication volume from an arbitrary first core s to an arbitrary second core d by the summation of the data communication flow multiplication results, when the first core s is mapped to the first tile k and the second core d is mapped to the second tile l, in which proximity index values of the first and second tiles k and l are changed to the proximity index values of all tiles, the multiplication is carried out for the changed proximity index values;
- summing the communication volume multiplication results;
- carrying out the summation of the communication volume multiplication results calculations for all cores;
- and
- summing the calculations for all cores results, to thereby determine which of the first and second tiles k and l minimize the hop distance between the first and second switches i and j.
A computer-readable volatile and non-volatile medium encoded with a computer program executable by a computer to perform method steps of creating a tile-switch mapping architecture comprising:
- multiplying a data communication flow from an arbitrary first tile k to an arbitrary second tile l by a hop distance value between arbitrary first and second switches i and j, in which the hop distance value of the first and second switches i and j is changed to the hop distance values of switches abutting the first tile k and switches abutting the second tile l, the multiplication is carried out for the changed hop distance values;
- summing the data communication flow multiplication results;
- multiplying a communication volume from an arbitrary first core s to an arbitrary second core d by the summation of the data communication flow multiplication results, when the first core s is mapped to the first tile k and the second core d is mapped to the second tile l, in which proximity index values of the first and second tiles k and l are changed to the proximity index values of all tiles, the multiplication is carried out for the changed proximity index values;
- summing the communication volume multiplication results;
- carrying out the summation of the communication volume multiplication results calculations for all cores;
- and
- summing the calculations for all cores results, to thereby determine the first and second tiles k and l which minimize the hop distance between the first and second switches i and j.
A method of creating a tile-switch mapping architecture comprising:
- calculating a sum of products of data communication flow and hop distance between switches abutting tiles;
- calculating a sum of products of data communication volumes and the sum of products of data communication flow and hop distance between switches abutting tiles for tiles mapped to cores;
- repeating the step of calculating a sum of products of data communication volumes and the sum of products of data communication flow and hop distance between switches abutting tiles for tiles mapped to cores for all cores;
- and
- summing the calculations for all cores results, to determine a minimum hop distance between switches.
Dependencies are inferred from the claim text.