Optimizing mode register set commands
AssigneeIntel Corporation
InventorsChristopher Cox, Howard S. David
Life of this patent
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Abstract
In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency.
Claims14
A method comprising:
- generating a mode register set (MRS) decoded signal to identify presence of a MRS command on a memory command bus targeted towards a mode register of a memory;
- delaying a first signal for a predetermined delay and disabling address inversion in a register device using the delayed first signal;
- switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles in the register device, wherein the address inversion is disabled for at least a portion of the predetermined number of clock cycles;
- performing an MRS command to the mode register in one or more dynamic random access memory (DRAM) devices responsive to the earlier MRS command to the register device, during the predetermined number of clock cycles;
- and
- switching back to the first command timing frequency.
An apparatus comprising:
- a mode register set (MRS) command decoder to generate a first signal to identify presence of a MRS command in a register device of a memory;
- at least one delay stage to delay the first signal for a predetermined delay;
- a first logic to disable address inversion responsive to the delayed first signal;
- and
- a second logic to switch from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles responsive to the first signal, wherein the address inversion is disabled for at least a portion of the predetermined number of clock cycles, perform the MRS command to a mode register in one or more dynamic random access memory (DRAM) devices responsive to the MRS command during the predetermined number of clock cycles, and switch back to the first command timing frequency.
Dependencies are inferred from the claim text.