Semiconductor memory device containing antifuse write voltage generation circuit
AssigneeFujitsu Microelectronics Limited
InventorHiroyoshi Tomita
Life of this patent
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Abstract
A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which the first internal power supply is supplied, an antifuse memory for writing predetermined information, and also a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage.
Claims16
A semiconductor memory device to which an external power supply voltage is applied, comprising:
- a first internal power supply generation circuit that boosts the external power supply voltage to generate a first internal power supply;
- a memory core to which the first internal power supply is supplied;
- an antifuse memory in which predetermined information is written;
- and
- a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage,
- wherein writing to an antifuse of the antifuse memory is performed by applying the antifuse write voltage thereto,
- wherein the first internal power supply generation circuit boosts the first internal power supply to a first potential when the memory is in an active state, and
- wherein the semiconductor memory device includes an antifuse write control circuit for controlling the first internal power supply generation circuit so that the first internal power supply boosts to a second potential that is higher than the first potential during antifuse writing.
A semiconductor memory device to which an external power supply voltage is applied, comprising
- a first internal power supply generation circuit that boosts the external power supply voltage to generate a first internal power supply;
- a second internal power supply generation circuit that generates a second internal power supply that is lower than the first internal power supply from the external power supply voltage;
- a memory core having a memory array in which a word line is driven by the first internal power supply and the second internal power supply is connected to a capacitor of a memory cell;
- an antifuse memory in which defective bit remedy information located in the memory array is written;
- and
- a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage,
- wherein the antifuse write voltage is applied to an antifuse of the antifuse memory to perform writing thereto,
- wherein the first internal power supply generation circuit boosts the first internal power supply to a first potential when the memory is in an active state, and
- wherein the semiconductor memory device includes an antifuse write control circuit for controlling the first internal power supply generation circuit so that the first internal power supply boosts to a second potential that is higher than the first potential during antifuse writing.
A semiconductor memory device to which an external power supply voltage is applied, comprising:
- a first internal power supply generation circuit that boosts the external power supply voltage to generate a first internal power supply;
- a memory core to which the first internal power supply is supplied;
- an antifuse memory in which predetermined information is written;
- and
- a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage,
- wherein writing to an antifuse of the antifuse memory is performed by applying the antifuse write voltage thereto
- wherein the first internal power supply generation circuit operates in a slow mode where a response speed for generating the first internal power supply is decreased when the memory is in a standby state, and operates in a fast mode where the response speed is increased when the memory is in an active state.
Dependencies are inferred from the claim text.