Memory device having a read pipeline and a delay locked loop

A memory device having a memory core, the memory device comprising:

• a first interface to receive control signals including a control signal that specifies a read operation;
• a second interface to output read data in response to receipt of the control signal that specifies the read operation, the second interface including a receiver circuit to receive write data after the memory device receives a control signal that specifies a write operation;
• a delay locked loop circuit to receive an external clock signal, the delay locked loop circuit to generate an internal clock signal using the external clock signal, wherein the memory device is configured to provide the internal clock signal to the receiver circuit in response to receipt of the control signal that specifies the write operation, the internal clock signal to be used in receiving the write data;
• and
• a read pipeline circuit to provide the read data accessed from the memory core to the second interface, wherein the internal clock signal is provided to the read pipeline circuit in response to receipt of the control signal that specifies the read operation at the first interface.

A system comprising:

• a memory controller;
• a memory device, coupled to the memory controller, the memory device including:
• a memory core;
• a delay locked loop circuit to receive an external clock signal, the delay locked loop circuit to generate an internal clock signal using the external clock signal;
• a read pipeline circuit to provide read data accessed from the memory core to an external signal line, wherein the internal clock signal is provided to the read pipeline circuit in response to receipt of a signal from the memory controller that specifies a read operation;
• and
• a receiver circuit to receive write data after the memory device receives a signal from the memory controller that specifies a write operation, wherein the memory device is configured to provide the internal clock signal to the receiver circuit in response to receipt of the signal from the memory controller that specifies the write operation;
• a first set of signal lines to transfer data between the memory device and the memory controller, wherein the external signal line is included in the first set of signal lines;
• and
• a second set of signal lines to provide the signal that specifies the read operation from the memory controller to the memory device.