US 7,626,878 B1Granted

Active bit line charge keeper

AssigneeNVIDIA Corporation

InventorsHwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young

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Abstract

One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge keeper circuit includes two sub-circuits, each disposed between bit line pairs within the SRAM circuit. The first sub-circuit mitigates residual state associated with over-developed read state on the bit lines. The second sub-circuit mitigates the effects of residual state associated with reading one value on a given pair of bit lines and subsequently writing a different value. By mitigating the effects of residual state within an SRAM circuit, higher reliability at a given performance level may be achieved.

Claims20

Dependent claims

A two-port static random access memory (SRAM) circuit, comprising:

control logic configured to receive a reference clock signal and to transmit a read address, a write address and a read-write select signal;
a shared address decoder configured to receive the read address, the write address and the read-write select signal from the control logic and to assert a word line signal;
a single-port memory array configured to receive the asserted word line signal from the shared address decoder;
and
a read/write input/output unit configured to read data from and write data to the single-port memory array and including an active bit line charge keeper configured to increase a second differential voltage between the first bit line and the second bit line to achieve a differential state change and reduce a first differential voltage developed on a first bit line and a second bit line during a read cycle by activating a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the positive supply voltage and the second transistor is coupled between the second bit line and the positive supply voltage with a gate of the first transistor coupled to a gate of the second transistor to restore the first bit line and the second bit line between read and write cycles.

2 more elements

An integrated circuit, comprising:

a plurality of input/output circuits;
core logic;
and a static random access memory (SRAM) unit that includes a two-port SRAM circuit that comprises:
control logic configured to receive a reference clock signal and to transmit a read address, a write address and a read-write select signal;
a shared address decoder configured to receive the read address, the write address and the read-write select signal from the control logic and to assert a word line signal;
a single-port memory array configured to receive the asserted word line signal from the shared address decoder;
and
a read/write input/output unit configured to read data from and write data to the single-port memory array and including an active bit line charge keeper configured to increase a second differential voltage between the first bit line and the second bit line to achieve a differential state change and to reduce a first differential voltage developed on a first bit line and a second bit line during a read cycle by activating a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the positive supply voltage and the second transistor is coupled between the second bit line and the positive supply voltage with a gate of the first transistor coupled to a gate of the second transistor to restore the first bit line and the second bit line between read and write cycles.

5 more elements

Dependencies are inferred from the claim text.