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US 7,626,877 B2Granted
Low voltage sense amplifier and sensing method
AssigneeMicron Technology, Inc.
InventorsTae Kim, Charles L. Ingalls, David Pinney, Howard Kirsch
Life of this patent
Estimating the term…
Abstract
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
Claims20
A memory device comprising:
- a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
- a column address circuit operable to receive and decode column address signals applied to the external address terminals;
- at least one array of memory cells arranged in rows and columns, each of the memory cells having a location determined by the decoded row address signals and the decoded column address signals;
- a plurality of sense amplifiers coupled to respective columns of memory cells in the at least one array, each of the sense amplifiers comprising a latch circuit coupled to the respective column and configured to latch a data state of a memory cell coupled to the digit line and further configured to generate differential data signals in response to the data state, the differential data signals having first and second voltages;
- a first voltage supply circuit coupled to the latch circuit of at least one sense amplifier and configured to provide a positive voltage as the first voltage;
- a second voltage supply circuit coupled to the latch circuit of at least one sense amplifier and configured to provide a negative voltage as the second voltage;
- a data path circuit operable to couple data signals corresponding to the data states between the sense amplifiers and external data terminals of the memory device;
- and
- a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.
6 more elements
A memory device comprising:
- a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
- a column address circuit operable to receive and decode column address signals applied to the external address terminals;
- at least one array of memory cells arranged in rows and columns, each of the memory cells having a location determined by the decoded row address signals and the decoded column address signals, each column having at least one digit line;
- a plurality of sense amplifiers coupled to the digit line of the respective columns of memory cells in the at least one array, each of the sense amplifiers comprising:
- a latch circuit having a node and configured to latch a data state from the respective digit line coupled to the node and further configured to generate differential data signals in response to the data state;
- and
- a coupling circuit coupled to the node of the latch and to the respective digit line, the coupling circuit configured to couple the respective digit line to the node of the latch responsive a control signal;
- a control circuit coupled to the coupling circuit of at least one sense amplifier and configured to control the coupling circuit to couple the respective digit line to the node and decouple the respective digit line and the node during a first phase and further configured to control the coupling circuit to couple the respective digit line to the node during a second phase subsequent to the first phase, the respective digit line and the node coupled at a controlled rate during the second phase;
- a data path circuit operable to couple data signals corresponding to the data states between the sense amplifiers and external data terminals of the memory device;
- and
- a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.
8 more elements
A processor-based system, comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;
- an output device coupled to the processor through the processor bus to allow data to be output from the computer system;
- a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device;
- a memory controller coupled to the processor through the processor bus;
- and
- a memory device coupled to the memory controller, the memory device comprising:
- a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
- a column address circuit operable to receive and decode column address signals applied to the external address terminals;
- at least one array of memory cells arranged in rows and columns, each of the memory cells having a location determined by the decoded row address signals and the decoded column address signals;
- a plurality of sense amplifiers coupled to respective columns of memory cells in the at least one array, each of the sense amplifiers comprising a latch circuit coupled to the respective column and configured to latch a data state of a memory cell coupled to the digit line and further configured to generate differential data signals in response to the data state, the differential data signals having first and second voltages;
- a first voltage supply circuit coupled to the latch circuit of at least one sense amplifier and configured to provide a positive voltage as the first voltage;
- a second voltage supply circuit coupled to the latch circuit of at least one sense amplifier and configured to provide a negative voltage as the second voltage;
- a data path circuit operable to couple data signals corresponding to the data states between the sense amplifiers and external data terminals of the memory device;
- and
- a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.
13 more elements
A processor-based system, comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;
- an output device coupled to the processor through the processor bus to allow data to be output from the computer system;
- a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device;
- a memory controller coupled to the processor through the processor bus;
- and
- a memory device coupled to the memory controller, the memory device comprising:
- a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
- a column address circuit operable to receive and decode column address signals applied to the external address terminals;
- at least one array of memory cells arranged in rows and columns, each of the memory cells having a location determined by the decoded row address signals and the decoded column address signals, each column having at least one digit line;
- a plurality of sense amplifiers coupled to the digit line of the respective columns of memory cells in the at least one array, each of the sense amplifiers comprising:
- a latch circuit having a node and configured to latch a data state from the respective digit line coupled to the node and further configured to generate differential data signals in response to the data state;
- and
- a coupling circuit coupled to the node of the latch and to the respective digit line, the coupling circuit configured to couple the respective digit line to the node of the latch responsive a control signal;
- a control circuit coupled to the coupling circuit of at least one sense amplifier and configured to control the coupling circuit to couple the respective digit line to the node and decouple the respective digit line and the node during a first phase and further configured to control the coupling circuit to couple the respective digit line to the node during a second phase subsequent to the first phase, the respective digit line and the node coupled at a controlled rate during the second phase;
- a data path circuit operable to couple data signals corresponding to the data states between the sense amplifiers and external data terminals of the memory device;
- and
- a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.
15 more elements
Dependencies are inferred from the claim text.