Semiconductor memory device and its test method
AssigneeYamaha Corporation
InventorYukichi Ono
Life of this patent
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Abstract
A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write and the test circuit sets data to this selected bit line. The other bit line is used for data read, and the written data is set to this bit line in the normal operation. Whether each memory core is not defective is judged by EOR which confirms data set to the bit line and data set to the inverted bit line are mutually inverted each other. A test method is realized which can test a defect of each memory core of a semiconductor memory such as SRAM in a short time.
Claims9
A test method for a memory device comprising steps of:
- (a) preparing a memory device including:
- a plurality of memory elements disposed in columns;
- word lines to which a select signal is applied to allow data to be input to and output from a predetermined one of said plurality of memory elements;
- and bit lines and inverted bit lines connected to said plurality of memory elements and input with signals having mutually inverted logic levels when data is to be written to the memory element selected by said select signal;
- (b) selecting a memory element;
- (c) inputting an input signal for test to said bit line of the memory element selected at said step (b), outputting an output signal corresponding to said test input signal from said inverted bit line, and detecting whether said input and output signals correspond to data having mutually inverted logic levels;
- (d) repeating said steps (b) and (c) by changing the memory element to be selected by said step (b) to select all of said plurality of memory elements;
- (e) after said step (d), selecting a memory element;
- (f) inputting an input signal for test to said inverted bit line of the memory element selected at said step (e), outputting an output signal corresponding to said test input signal from said bit line, and detecting whether said input and output signals correspond to data having mutually inverted logic levels;
- and
- (g) repeating said steps (e) and (f) by changing the memory element to be selected by said step (e) to select all of said plurality of memory elements.
Dependencies are inferred from the claim text.