Multi-wordline test control circuit and controlling method thereof
AssigneeHynix Semiconductor Inc.
InventorsHi-Hyun Han, Jee-Yul Kim
Life of this patent
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Abstract
A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.
Claims25
A multi-wordline test control circuit for a semiconductor integrated device, for performing a multi-wordline test, comprising:
- a multi-test control block configured to generate a first test signal and a second test signal in response to a multi-wordline test signal and a bank active signal;
- and
- a multi-wordline test block coupled with the multi-test control block, the multi-wordline test block configured to perform the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.
A method for controlling a multi-wordline test control circuit, comprising the steps of:
- generating a first test signal when a multi-wordline test signal is activated and a bank active signal is activated;
- deactivating a second test signal when the first test signal is activated;
- receiving some of a plurality of row addresses in response to the activated first test signal and deactivating first address decoding signals;
- generating second address decoding signals by decoding addresses associated with selection of mats among the row addresses in response to the deactivation of the second test signal such that only the second address decoding signals inputted to mats corresponding to the addresses associated with selection of mats are activated, and the second address decoding signals inputted to the other mats are deactivated;
- receiving the second address decoding signals and the second test signal and generating wordline off control signals for controlling a wordline driver;
- and
- receiving the first address decoding signals and the wordline off control signals and activating word lines.
A multi-wordline test control circuit comprising:
- a first multi-test control block arranged in a first bank and configured to generate multi-wordline test signals for respective cell mats in the first bank in response to a first bank active signal;
- a first multi-wordline test block coupled with the first multi-test control block and arranged in the first bank, and driven in response to the multi-wordline test signals for the respective cell mats in the first bank;
- a second multi-test control block arranged in a second bank and configured to generate multi-wordline test signals for respective cell mats in the second bank in response to a second bank active signal;
- and
- a second multi-wordline test block coupled with the first multi-test control block and arranged in the second bank, and driven in response to the multi-wordline test signals for the respective cell mats in the second bank,
- wherein a multi-wordline test is performed for at least one of the banks or for at least one of the cell mats of the banks.
Dependencies are inferred from the claim text.