Semiconductor memory apparatus, semiconductor integrated circuit having the same, and method of outputting data in semiconductor memory apparatus

A semiconductor memory apparatus comprising:

• a data output unit configured to separately buffer rising data and falling data in response to a rising clock and a falling clock, thereby outputting final rising output data and final falling output data to a rising output data pad and a falling data output pad, respectively;
• and
• a data output strobe signal generation unit configured to separately buffer the rising clock and the falling clock, thereby outputting a rising data output strobe signal and a falling data output strobe signal.

A semiconductor integrated circuit comprising:

• a semiconductor memory apparatus configured to buffer rising data in synchronization with a rising clock in response to a rising output enable signal to obtain buffered rising data and to output the buffered rising data through a rising output data pad, and to buffer falling data in synchronization with a falling clock in response to a falling output enable signal to obtain buffered falling data and to output the buffered falling data through a falling output data pad;
• and
• a memory control apparatus configured to receive the buffered rising data output from the rising output data pad and the buffered falling data output from the falling output data pad, and to perform a data recovery operation.

A method of outputting data in a semiconductor memory apparatus, the method comprising:

• generating rising output data from rising data in response to a rising clock and a rising output enable signal, and generating falling output data from falling data in response to a falling clock and a falling output enable signal;
• and
• buffering the rising output data using a first buffer and buffering the falling output data using a second buffer, thereby outputting final rising output data and final falling output data to a rising output data pad and a falling output data pad, respectively.