Semiconductor memory device and its driving method
AssigneeHynix Semiconductor Inc.
InventorSung-Joo Ha
Life of this patent
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Abstract
A semiconductor memory device includes a data transfer line for read, a data signal transfer unit, a reset controller, and a data signal transfer unit for write. The data signal transfer unit for read receives a first data signal corresponding to a read command via the data transfer line and outputs the first data signal. The reset controller resets the data transfer line in response to a reset signal. The data signal transfer unit for write receives a second data signal corresponding to a write command, and outputs the second data signal to the data transfer line. The data transfer line is reset in response to the reset signal.
Claims19
A semiconductor memory device comprising:
- a first data transfer line;
- a second data transfer line;
- a read data transfer unit for receiving a first data signal corresponding to a read command and outputting the first data signal to the first data transfer line;
- a reset controller for resetting the second data transfer line in response to a reset signal;
- and
- a write data transfer unit for receiving a second data signal corresponding to a write command from and outputting the second data signal to the second data transfer line,
- wherein the write data transfer unit further resets the second data transfer line in response to the reset signal.
A semiconductor memory device comprising:
- a data transfer line;
- a read data signal transfer unit for receiving a first data signal corresponding to a read command and outputting the first data signal, wherein the first data signal is transmitted from the data transfer line;
- a reset controller for resetting the data transfer line in response to a reset signal;
- and
- a write data signal transfer unit for receiving a second data signal corresponding to a write command and outputting the second data signal to the data transfer line,
- wherein the write data signal transfer unit further resets the data transfer line in response to the reset signal.
A semiconductor memory device comprising:
- a first data transfer line;
- a second data transfer line;
- a reset circuit for resetting the second data transfer line to a reset voltage in response to a reset signal;
- and
- a driver for driving data of the first data transfer line to the second data transfer line,
- wherein the driver resets the second data transfer line to the reset voltage in response to the reset signal.
Dependencies are inferred from the claim text.