NAND flash memory programming
AssigneeMicron Technology, Inc.
InventorsSeiichi Aritome, Haitao Liu, Di Li
Life of this patent
Estimating the term…
Abstract
A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.
Claims30
A method of programming a short channel source-side select gate NAND, comprising:
- adjusting a selected bitline voltage;
- adjusting unselected bitline voltages;
- adjusting drain select gate, pass, and program voltages by an equal amount to that of the selected bitline;
- and
- programming the NAND with the adjusted voltages.
A method of programming a short channel source-side select gate NAND, comprising:
- adjusting a selected bitline voltage to be approximately equal to a common source voltage, and greater than a well voltage for the NAND.
A method of programming a short channel source-side select gate NAND memory, comprising:
- adjusting a bitline voltage for a selected bitline by raising the voltage by a predetermined amount;
- adjusting a bitline voltage for a non-selected bitline by the predetermined amount;
- adjusting a drain select gate voltage, a pass voltage, and a program voltage for cells on the NAND string by the predetermined amount;
- and
- programming the NAND with the adjusted voltages.
A method of programming a short channel source-side select gate NAND memory, comprising:
- adjusting voltages of selected bitline, unselected bitline, drain select gate, pass, and program voltage of the NAND by a predetermined amount;
- and
- programming the NAND with the adjusted voltages.
A method of programming a short channel source-side select gate NAND, comprising:
- raising a selected bitline voltage by approximately 1.5 volts from a typical selected bitline programming voltage;
- raising unselected bitline voltages by approximately 1.5 volts from a typical unselected bitline programming voltage;
- raising drain select gate, pass, and program voltages by approximately 1.5 volts from typical drain select gate, pass, and program voltages;
- and
- programming the NAND with the raised voltages.
A method of programming a short channel source-side select gate NAND, comprising:
- biasing a selected bitline voltage to approximately 1.5 volts;
- biasing unselected bitline voltages to approximately 3.0 volts;
- biasing drain select gate for the selected NAND string to approximately 3.3 to 4.8 volts;
- biasing pass voltage for cells not to be programmed to approximately 10.5 volts;
- and
- biasing program voltage for a cell to be programmed to approximately 21.5 volts;
- and
- programming the NAND with the biased voltages.
A method of programming a short channel source-side select gate NAND memory, comprising:
- back biasing a tub or p-well of the NAND string;
- and
- programming the NAND with the back biased voltage, wherein the back bias voltage is approximately −1.5 volts.
A method of programming a short channel source-side select gate NAND memory, comprising:
- back biasing a tub or p-well of the NAND string;
- and
- programming the NAND with the back biased voltage, and further comprising:
- raising a select gate voltage for the drain select gate by a predetermined amount before programming.
A method of programming a short channel source-side select gate NAND memory, comprising:
- back biasing a tub or p-well of the NAND string to approximately −1.5 volts;
- raising a select gate voltage for a drain select gate by approximately 1.5 volts;
- and
- programming the NAND with the back biased voltage.
A method of programming a dual short channel source-side select gate NAND memory, comprising:
- adjusting a bitline voltage for a selected bitline by raising the voltage by a predetermined amount;
- adjusting a bitline voltage for a non-selected bitline by the predetermined amount;
- adjusting a first drain select gate voltage, a pass voltage, and a program voltage for cells on the NAND string by the predetermined amount;
- and
- programming the NAND with the adjusted voltages.
A method of programming a dual short channel source-side select gate NAND memory, comprising:
- adjusting a bitline voltage for a selected bitline by raising the voltage by a predetermined amount;
- adjusting a bitline voltage for a non-selected bitline by the predetermined amount;
- adjusting a first drain select gate voltage, a pass voltage, and a program voltage for cells on the NAND string by the predetermined amount;
- and
- programming the NAND with the adjusted voltages.
A method of programming a dual short channel source-side select gate NAND memory, comprising:
- back biasing a tub or p-well of the NAND string;
- and
- programming the NAND with the back biased voltage, wherein the back bias voltage is approximately −1.5 volts.
A method of programming a dual short channel source-side select gate NAND memory, comprising:
- back biasing a tub or p-well of the NAND string;
- and
- programming the NAND with the back biased voltage, and further comprising:
- raising a first drain select gate voltage for the drain select gate by a predetermined amount before programming.
A method of preventing punch through in a short channel source-side select gate NAND, comprising:
- biasing a selected bitline to approximately 1.5 volts;
- biasing unselected bitlines to approximately 3.0 volts;
- raising voltages on a drain select gate, cells not to be programmed, and cells to be programmed by approximately 1.5 volts;
- and
- programming with the biased and adjusted voltages.
Dependencies are inferred from the claim text.