Charge pump operation in a non-volatile memory device

A memory system comprising:

• a processor that generates memory signals;
• and
• a non-volatile memory device coupled to the processor and operating in response to the memory signals, the device comprising:
• a memory array comprising a plurality of memory cells arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line;
• a charge pump circuit coupled to the memory array for generating a programming voltage, the charge pump circuit comprising a charge pump for generating the programming voltage in response to an enable signal, a first load coupled to the charge pump, a second load coupled to the charge pump and to the first load;
• and
• a memory control circuitry coupled to the charge pump circuit for controlling operation of the charge pump circuit, the memory control circuitry configured to generate the enable signal during a programming operation prior to a data loading operation of the programming operation, the controller circuit is further configured to control charge sharing between the first and second loads such that a first load voltage is recharged without coupling to the charge pump during an initial portion of a programming cycle of the programming operation.

A memory module comprising:

• at least two memory devices, each comprising:
• a memory array comprising a plurality of memory cells arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line;
• a charge pump circuit coupled to the memory array for generating a programming voltage, the charge pump circuit comprising a charge pump for generating the programming voltage in response to an enable signal, a first load coupled to the charge pump, a second load coupled to the charge pump and to the first load;
• and
• a memory control circuitry coupled to the charge pump circuit for controlling operation of the charge pump circuit, the memory control circuitry configured to generate the enable signal during a programming operation prior to a data loading operation of the programming operation, the controller circuit is further configured to control charge sharing between the first and second loads such that a first load voltage is recharged without coupling to the charge pump during an initial portion of a programming cycle of the programming operation;
• and
• a plurality of contacts configured to provide selective contact between the at least two device and a host system.

A memory module comprising:

• a memory device comprising:
• a memory array comprising a plurality of memory cells arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line;
• a charge pump circuit coupled to the memory array for generating a programming voltage, the charge pump circuit comprising a charge pump for generating the programming voltage in response to an enable signal, a first load coupled to the charge pump, a second load coupled to the charge pump and to the first load;
• and
• a memory control circuitry coupled to the charge pump circuit for controlling operation of the charge pump circuit, the memory control circuitry configured to generate the enable signal during a programming operation prior to a data loading operation of the programming operation, the controller circuit is further configured to control charge sharing between the first and second loads such that a first load voltage is recharged without coupling to the charge pump during an initial portion of a programming cycle of the programming operation;
• a housing for enclosing the memory device;
• and
• a plurality of contacts coupled to the housing and configured to provide selective contact between the memory device and a host system.