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US 7,626,863 B2Granted
Flash memory array system including a top gate memory cell
AssigneeSilicon Storage Technology, Inc.
InventorsHieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Abstract
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
Claims20
A memory system comprising:
- a plurality of memory cells arranged in sectors,
- wherein top gates of memory cells in a sector are configured to program the memory cells and are coupled to a first line,
- wherein source lines of memory cells in the sector are coupled to a second line, and
- wherein each memory cell includes:
- a floating gate positioned for electrical coupling with a top gate of the top gates configured to program the memory cells,
- wherein each floating gate has a tip adjacent to the top gate for erasing the floating gate through the tip to the top gate.
3 more elements
A memory system comprising:
- a plurality of memory cells arranged in sectors,
- wherein source lines of memory cells in a sector being coupled to a first line, and
- top gate lines of memory cells in said sector are configured to program the memory cells and are coupled to individual lines,
- wherein each memory cell includes:
- a floating gate positioned for electrical coupling with a top gate of the top gates lines configured to program the memory cells,
- wherein each floating gate has a tip adjacent to the top gate for erasing the floating gate through the tip to the top gate.
3 more elements
Dependencies are inferred from the claim text.