Semiconductor memory device
AssigneeElpida Memory, Inc.
InventorYasushi Matsubara
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Abstract
A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.
Claims7
A semiconductor memory device comprising:
- a memory cell array having a hierarchical word line structure including a plurality of main word lines and a plurality of sub-word lines;
- a main word driver for driving a non-selected main word line to a high level and for driving and activating a selected main word line to a low level;
- and
- a sub-word driver having at least a PMOS transistor to a gate of which the main word line is connected, said sub-word driver for selectively activating the sub-word line corresponding to the selected main word line,
- wherein said memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in each area other than the predetermined area.
Dependencies are inferred from the claim text.