US 7,626,850 B2Granted

Systems and devices for implementing sub-threshold memory devices

AssigneeTexas Instruments Incorporated

InventorsCharles M. Branch, Steven C. Bartling

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Abstract

Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input. The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor. In addition, the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor by the first inverter, and the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor by the second inverter.

A sub-threshold memory device, the memory device comprising:

a bit cell, wherein the bit cell includes:
a bit line input;
a word line input;
a first PMOS transistor having a gate, a source and a drain, wherein the source of the first PMOS transistor is electrically coupled to the bit line input, and wherein the gate of the first PMOS transistor is electrically coupled to the word line input;
a second PMOS transistor having a gate, a source and a drain, wherein the source of the second PMOS transistor is electrically coupled to the bit line input, and wherein the gate of the second PMOS transistor is coupled to the word line input, and wherein the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor;
a first NMOS transistor having a gate, a source and a drain, wherein the source of the first NMOS transistor is electrically coupled to the bit line input, and wherein the gate of the first NMOS transistor is electrically coupled to the word line input;
a second NMOS transistor having a gate, a source and a drain, wherein the source of the second NMOS transistor is electrically coupled to the bit line input, and wherein the gate of the second NMOS transistor is electrically coupled to the word line input, and wherein the drain of second NMOS transistor is electrically coupled to the drain of the first NMOS transistor;
a first inverter, wherein the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor through the first inverter;
a second inverter, wherein the drain of the first NMOS transistor is electrically coupled to the drain of the second NMOS transistor through the second inverter;
a word line driver that is electrically coupled to the word line input;
and
a read port that is electrically coupled to the drains of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor, wherein the read port receives a read enable signal that indicates when the bit cell is being written, and wherein the read port further comprises:
a first tri-state buffer that is coupled to the drains of the first NMOS transistor and the first PMOS transistor, wherein the first tri-state buffer is adapted to receive the read enable signal;
and
a second tri-state buffer that is coupled to the drains of the second NMOS transistor and the second PMOS transistor, wherein the second tri-state buffer is adapted to receive the read enable signal.

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Abstract

Claims3