Memory device, motion vector detection device, and detection method

A memory device comprising:

• a first frame memory portion including a plurality of memory cells connected to bit lines and word lines, respectively, and arranged in a matrix, to store an image signal of a first frame;
• and
• a second frame memory portion including a plurality of memory cells connected to the bit lines and word lines, respectively, and arranged in the matrix, to store an image signal of a second frame,
• wherein the first frame memory portion and the second frame memory portion are formed consecutively in a row direction, in which the bit lines extend;
• wherein, in the first frame memory portion and the second frame memory portion, charges accumulated in capacitors of a plurality of memory cells connected to a plurality of activated word lines can be combined along one bit line, the plurality of memory cells connected to the one bit line including cells having different maximum predetermined capacitance of their capacitors;
• wherein, in each of the first frame memory portion and the second frame memory portion, the plurality of memory cells connected to each of the bit lines is divided into units, each including a predetermined number of memory cells that are connected to a predetermined number of word lines, to store one item of pixel data in each of these divided units;
• wherein each unit of the first frame memory portion stores pixel data of the image signal of the first frame in straight binary format and each unit of the second frame memory portion stores pixel data of the image signal of the second frame in two's complement format, and
• wherein the memory device further comprises:
• activation means for simultaneously activating a plurality of word lines related to predetermined data in the first frame memory portion and a plurality of word lines related to predetermined data in the second frame memory portion;
• bit line selection means for selecting any one of the plurality of bit lines;
• and
• signal output means for outputting a digital signal having a value that corresponds to a total amount of charges obtained along the bit line selected by the bit line selection means.

A memory device comprising:

• a memory portion including a plurality of memory cells connected to bit lines and word lines, respectively, and arranged in a matrix,
• wherein, in the memory portion, charges accumulated in capacitors of a plurality of memory cells connected to a plurality of activated word lines can be combined along one bit line, the plurality of memory cells connected to the one bit line including cells having different maximum predetermined capacitance of their capacitors;
• and
• wherein, in the memory portion, the plurality of memory cells connected to each of the bit lines is divided into units, each including a predetermined number of memory cells that are connected to a predetermined number of word lines, to store one item of data in each of these divided units,
• the memory device further comprising:
• activation means for simultaneously activating word lines related to plural items of data;
• bit line selection means for selecting any one of the plurality of bit lines;
• and
• signal output means for outputting a digital signal having a value that corresponds to a total amount of charges obtained along the bit line selected by the bit line selection means.

A memory device allowing charges accumulated in capacitors of a plurality of memory cells connected to a plurality of activated word lines to be combined along one bit line, the device comprising:

• an activation unit configured to activate the plurality of word lines simultaneously;
• and
• a signal output unit configured to output a digital signal having a value that corresponds to a total amount of charges obtained along the one bit line by combining the charges accumulated in the capacitors of the plurality of memory cells connected to the plurality of word lines activated by the activation unit,
• wherein the plurality of memory cells connected to the one bit line includes cells having different maximum predetermined capacitance of their capacitors.

A memory device comprising:

• a first frame memory portion including a plurality of memory cells connected to bit lines and word lines, respectively, and arranged in a matrix, and configured to store an image signal of a first frame;
• and
• a second frame memory portion including a plurality of memory cells connected to the bit lines and word lines, respectively, and arranged in the matrix, and configured to store an image signal of a second frame,
• wherein the first frame memory portion and the second frame memory portion are formed consecutively in a row direction, in which the bit lines extend;
• wherein, in the first frame memory portion and the second frame memory portion, charges accumulated in capacitors of a plurality of memory cells connected to a plurality of activated word lines are configured to be combined along one bit line, the plurality of memory cells connected to the one bit line including cells having different maximum predetermined capacitance of their capacitors;
• wherein, in each of the first frame memory portion and the second frame memory portion, the plurality of memory cells connected to each of the bit lines is divided into units, each including a predetermined number of memory cells that are connected to a predetermined number of word lines, and configured to store one item of pixel data in each of these divided units;
• wherein each unit of the first frame memory portion is configured to store pixel data of the image signal of the first frame in straight binary format and each unit of the second frame memory portion is configured to store pixel data of the image signal of the second frame in two's complement format, and
• wherein the memory device further comprises:
• an activation unit configured to simultaneously activate a plurality of word lines related to predetermined data in the first frame memory portion and a plurality of word lines related to predetermined data in the second frame memory portion;
• a bit line selection unit configured to select any one of the plurality of bit lines;
• and
• a signal output unit configured to output a digital signal having a value that corresponds to a total amount of charges obtained along the bit line selected by the bit line selection unit.

A memory device comprising:

• a memory portion including a plurality of memory cells connected to bit lines and word lines, respectively, and arranged in a matrix,
• wherein, in the memory portion, charges accumulated in capacitors of a plurality of memory cells connected to a plurality of activated word lines are configured to be combined along one bit line, the plurality of memory cells connected to the one bit line including cells having different maximum predetermined capacitance of their capacitors;
• and
• wherein, in the memory portion, the plurality of memory cells connected to each of the bit lines is divided into units, each including a predetermined number of memory cells that are connected to a predetermined number of word lines, and configured to store one item of data in each of these divided units,
• the memory device further comprising:
• an activation unit configured to simultaneously activate word lines related to plural items of data;
• a bit line selection unit configured to select any one of the plurality of bit lines;
• and
• a signal output unit configured to output a digital signal having a value that corresponds to a total amount of charges obtained along the bit line selected by the bit line selection unit.