Inverter circuit with switching deadtime synchronized sample and hold current detection

An inverter device comprising:

• an inverter circuit including pairs of upper and lower arms provided in association with respective plural phases, the inverter circuit being constituted such that the respective arm has a switching device and a diode connected in parallel with the switching device, the respective lower arm for the respective phase has a phase-current detection resistance provided in serial to the switching device for detecting a phase current in a motor, and a voltage for driving the motor is extracted from a connection point between the upper and lower arms for the respective phase;
• a PWM circuit for supplying a PWM (Pulse Width Modulation) signal having a predetermined duty ratio to the respective switching device in the inverter circuit;
• and
• a sample-and-hold circuit for, when the switching device in the lower arm is on by the PWM signal from the PWM circuit, sampling a voltage across the phase-current detection resistance induced by an electric current flowing through the switching device and sampling and holding the sampled voltage;
• wherein
• during a dead time period when both the respective switching devices in the upper arm and the lower arm for one of the phases are off, the sample-and-hold circuit samples the voltage across the phase-current detection resistance inducted by the electric current flowing through the diode connected in parallel with the switching device in the lower arm, and samples and holds the sampled voltage.