US 7,624,366 B2 · Clock aware placement

Abstract

The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

Claims34

Dependent claims

A computer-implemented method of designing a layout for a plurality of latches in a common clock domain of an integrated circuit, comprising:

placing the latches in a first layout by executing first instructions on a computer system;
building at least one star object for the latches in the first layout by executing second instructions on the computer system, the star object representing an interim clock structure for the clock domain;
weighting the latches based on wire distance from a source of the star object by executing third instructions on the computer system;
and
placing the latches in a second layout using the latch weighting by executing fourth instructions on the computer system.

2 more elements

Dependencies are inferred from the claim text.

Clock aware placement

Life of this patent

Clock aware placement

Life of this patent

Abstract

Claims34