Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes

A computer system for performing equivalence checking on logic circuit designs having differing clocking and latching schemes, said computer system comprising:

• for an original and modified versions of an integrated logic circuit design,
• means for converting level-sensitive sequential elements sensitized by a clock=0 into buffers;
• means for converting level-sensitive sequential elements sensitized by a clock=1 into level-sensitive registers;
• means for selectively transforming a subset of edge-sensitive sequential elements to level-sensitive sequential elements by removing edge detection logic from said subset of edge-sensitive sequential elements;
• and
• means for setting a clock to said sequential elements to a logical “1” to verify sequential equivalences of said original and modified versions of said integrated logic circuit design;
• and
• means for generating by said computer system an indication of sequential equivalence of said original and modified versions of said integrated logic circuit design.