US 7,624,329 B2 · Programming a memory device having error correction logic

Abstract

Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.

Claims20

Dependent claims

A method for programming a non-volatile memory array comprising addressable units, wherein each of the addressable units is configured to store at least a main portion and an error correction portion, the method comprising:

in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode, wherein in the error correction disabled mode at least one main array bit corresponding to data to be stored in the main portion of at least one addressable unit of the non-volatile memory array is generated and programming at least the main portion of the at least one addressable unit of the non-volatile memory array in the error correction disabled mode;
and
in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.

An apparatus for programming a non-volatile memory array comprising addressable units, wherein each of the addressable units is configured to store at least a main portion and an error correction portion, the apparatus comprising:

at least one buffer for receiving data for storage in the main portion of at least one addressable unit;
and
an error correction code logic configured to generate error correction bits for storage in the error correction portion corresponding to the data for programming in the main portion, wherein the error correction code logic is enabled or disabled in response to a control signal from a controller coupled to the non-volatile memory array, and wherein the apparatus is configured to operate in an error correction fill mode during which the error correction code logic is enabled such that the error correction code logic is used to generate at least one error correction bit for programming in the error correction portion of the at least one addressable unit.

Dependencies are inferred from the claim text.

Programming a memory device having error correction logic

Life of this patent

Programming a memory device having error correction logic

Life of this patent

Abstract

Claims20