Method and apparatus for automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number

#1. Field of the Invention

#The present invention relates generally to integrated circuit chips. In particular, the present invention relates to manufacturing and testing of integrated circuit chips. Still more particularly, the present invention relates to automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number.

#2. Description of the Related Art

#The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

#FIG. 1 is a block diagram of a data processing system in which aspects of the present invention may be implemented;

#FIG. 2 is a diagram illustrating two functionally equivalent parts with multiple replicated sub-components that are partially defective is depicted in accordance with an illustrative embodiment of the present invention;

#With reference now to the figures, and in particular with reference to FIG. 1, a block diagram of a data processing system in which the present invention may be implemented is depicted. Data processing system 100 may be a symmetric multiprocessor (SMP) system including a plurality of processors 101-104, which connect to system bus 106. For example, data processing system 100 may be an IBM® eServer™, a product of International Business Machines Corporation in Armonk, N.Y., implemented as a server within a network. Alternatively, a single processor system may be employed. Also connected to system bus 106 is memory controller 108, which provides an interface to a plurality of local memories 160-163. I/O bus bridge 110 connects to system bus 106 and provides an interface to I/O bus 112. Memory controller 108 and I/O bus bridge 110 may be integrated as depicted.

#Data processing system 100 is a logical partitioned (LPAR) data processing system. Thus, data processing system 100 may have multiple heterogeneous operating systems (or multiple instances of a single operating system) running simultaneously. Each of these multiple operating systems may have any number of software programs executing within it. Data processing system 100 is logically partitioned such that different PCI I/O adapters 120-121, 128-129, and 136, graphics adapter 148, and hard disk adapter 149 may be assigned to different logical partitions. In this case, graphics adapter 148 connects to a display device (not shown), while hard disk adapter 149 connects to and controls hard disk 150.

#Thus, for example, suppose data processing system 100 is divided into three logical partitions, P1, P2, and P3. Each of PCI I/O adapters 120-121, 128-129, 136, graphics adapter 148, hard disk adapter 149, each of processors 101-104, and memory from local memories 160-163 is assigned to each of the three partitions. In these examples, local memories 160-163 may take the form of dual in-line memory modules (DIMMs). DIMMs are not normally assigned on a per DIMM basis to partitions. Instead, a partition will get a portion of the overall memory seen by the platform. For example, processor 101, some portion of memory from local memories 160-163, and I/O adapters 120, 128, and 129 may be assigned to logical partition P1; processors 102 and 103, some portion of memory from local memories 160-163, and PCI I/O adapters 121 and 136 may be assigned to partition P2; and processor 104, some portion of memory from local memories 160-163, graphics adapter 148, and hard disk adapter 149 may be assigned to logical partition P3.