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US 7,624,297 B2Granted
Architecture for a physical interface of a high speed front side bus
AssigneeInternational Business Machines Corporation
InventorsSteven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
Life of this patent
Estimating the term…
Abstract
A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
Claims17
A computer system comprising:
- a central processor unit (CPU) with a CPU front side bus (FSB) connected to a channel;
- a graphics processor unit (GPU) with a GPU FSB connected to the channel;
- and
- wherein the CPU FSB comprises a physical layer that receives a parallel data input from a plurality of receiver cores connected to the channel, and wherein the receiver cores comprise:
- a clock slice block having an analog portion and a digital portion, wherein the analog portion includes a filter that generates an unrotated in-phase clock (I) and Quadrature clock (Q), a phase rotator for creating a rotated I and Q clocks that is controlled by jitter control logic, and a mux for selecting between the unrotated I and Q clocks and the rotated I and Q clocks to output unrotated or rotated I and Q clocks;
- a plurality of data slice blocks having an analog portion and a digital portion;
- and
- a clock distribution block that distributes the selected rotated or unrotated I and Q clocks from the output of the mux to each copy of the data slice blocks.
5 more elements
A computer system comprising:
- a central processor unit (CPU) with a CPU front side bus (FSB) connected to an channel;
- a graphics processor unit (GPU) with a GPU FSB connected to the channel;
- and
- wherein the CPU FSB comprises a Physical layer that transmits data to the channel over a plurality of transmitter cores, and wherein the transmitter cores comprise:
- a plurality of data slice blocks having a digital portion and an analog portion;
- a clock slice block that outputs a compensated transmitter clock to the channel;
- a clock generation block having an analog portion and a digital portion;
- and
- a clock distribution block that distributes clocks from the clock generation block to each copy of the data slice block.
6 more elements
A computer game system comprising:
- a central processor unit (CPU) with a CPU front side bus (FSB) connected to an channel;
- a graphics processor unit (GPU) with a GPU FSB connected to the channel;
- and
- wherein the CPU FSB comprises a Physical layer that receives a parallel data input from a plurality of receiver cores connected to the channel and transmits data to the channel over a plurality of transmitter cores,
- wherein the receiver cores comprise:
- a clock slice block having an analog portion and a digital portion, wherein the analog portion includes a filter that generates an unrotated in-phase clock (I) and Quadrature clock (Q), a phase rotator for creating a rotated I and Q clocks that is controlled by jitter control logic, and a mux for selecting between the unrotated I and Q clocks and the rotated I and Q clocks to output unrotated or rotated I and Q clocks;
- a plurality of data slice blocks having an analog portion and a digital portion;
- a clock distribution block that distributes the selected rotated or unrotated I and Q clocks from the output of the mux to each copy of the data slice blocks;
- wherein the transmitter cores comprise:
- a plurality of data slice blocks having a digital portion and an analog portion;
- a clock slice block that outputs a compensated transmitter clock to the channel;
- a clock generation block having an analog portion and a digital portion;
- and
- a clock distribution block that distributes clocks from the clock generation block to each copy of the data slice block.
11 more elements
Dependencies are inferred from the claim text.