Processor system, instruction sequence optimization device, and instruction sequence optimization program
AssigneePanasonic Corporation
InventorsOsamu Taketoshi, Isao Tanaka, Toru Wada
Life of this patent
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AssigneePanasonic Corporation
InventorsOsamu Taketoshi, Isao Tanaka, Toru Wada
Estimating the term…
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.
A processor system including a plurality of processors, comprising:
Dependencies are inferred from the claim text.