Power management method of north bridge
AssigneeVIA Technologies, Inc.
InventorsRuei-Ling Lin, Jiin Lai, Hung-Yi Kuo
Life of this patent
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Abstract
A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.
Claims17
A power management method of a north bridge for managing power state of a processor and a main memory in a computer system, comprising:
- monitoring power state transition of the processor;
- accordingly adjusting operating clocks and operating voltages of the processor and the main memory utilizing a power state machine;
- and
- reducing operating clocks and operating voltages of the processor and the main memory, and pre-charging opened pages in the main memory if no memory access is detected, while the processor is at a rower saving state.
A computer system comprises:
- a processor;
- a north bridge connecting to the processor;
- a main memory connecting to the north bridge;
- a south bridge connecting to the north bridge;
- wherein the north bridge is in charge of power state management of the computer system, the north bridge reduces operating clocks and operating voltages of the processor and the main memory while the processor is at a power saving state, and the main memory is in a non-page mode.
A memory bridge with capable of power state management of a computer system, wherein the computer system further comprises a processor and a main memory system, the method comprises:
- a traffic monitor for monitoring power state transition of the processor;
- a power state machine determining to which power state the processor is transited according to the monitoring;
- and
- a power management control unit adjusting operating clocks and operating voltages of the processor and the main memory according to the power state machine and the determined power state,
- wherein, while the processor is at a rower saving state, the rower management control unit reduces operating clocks and operating voltages of the processor and of the main memory respectively, and the main memory is in a non-page mode.
Dependencies are inferred from the claim text.