System and method wherein conditional instructions unconditionally provide output

A method of executing a single conditional instruction via a pipelined processor employing a register renaming system dynamically mapping logical registers to physical registers, the method comprising:

• reading a prior value from a first physical register associated with a logical target register by the single conditional instruction, wherein the prior value is read irrespective of an evaluation outcome of a condition associated with the single conditional instruction, the prior value produced by an instruction distinct from the single conditional instruction;
• renaming the logical target register to a second physical register;
• performing an operation on one or more operand values to generate a result value prior to determining whether the condition is satisfied;
• and
• outputting a value of the single conditional instruction, wherein outputting comprises:
• writing the result value to the second physical register when the condition is satisfied;
• and
• writing the prior value to the second physical register when the condition is not satisfied.

A method of executing a single conditional instruction, the method comprising:

• reading a prior value from a logical target register irrespective of an evaluation of a condition associated with the single conditional instruction, the prior value produced by an instruction distinct from the single conditional instruction;
• performing an operation by the single conditional instruction on one or more operand values that generates a result;
• and
• outputting a value from the single conditional instruction, wherein outputting comprises:
• writing the result of the operation performed by the single conditional instruction to the logical target register when the condition is satisfied;
• and
• writing the prior value to the logical target register when the condition is not satisfied.

A processor comprising:

• a plurality of physical registers;
• a renaming table operative to dynamically associate logical register identifiers with the physical registers;
• and
• an instruction execution pipeline operative to execute a single conditional instruction to:
• read a prior value from a first physical register associated with a logical register identifier irrespective of an evaluation of a condition associated with the single conditional instruction, the prior value produced by an instruction distinct from the single conditional instruction;
• perform an operation on one or more operand values to generate a result;
• and
• provide the result when the condition is satisfied and provide the prior value when the condition is not satisfied.